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Sat, 17 May 2025 20:22:45 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 27/29] iommu/tegra241-cmdqv: Do not statically map LVCMDQs Date: Sat, 17 May 2025 20:21:44 -0700 Message-ID: <77e69ccee770b2b053a8cc6f15258926579e171c.1747537752.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|DS7PR12MB6096:EE_ X-MS-Office365-Filtering-Correlation-Id: 24b85be6-5619-4f10-501e-08dd95bb4a4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: 4D7B6BUOy+LjMjkAu0NMHllSuwX4XuwjGXSkyWbttaB/AWgd/UH3oWi8BtoEfVK8L+j+czOdzk9z7dkQrbjSaaj1G6roMRY+V39zqai5IY8/+40viyKCEf09kG+MptK9e+fYgz+a9nKGr3Mmo/xrrlX0tuwQfjxBQjFZxdYKLp6i9CXdWVmSpsVUYytpcFhyA7zEau96N1o3UDPn8WzxIP2MLYs7nYkx0Ca3P8MFtxEWTdknv9nGnX4G4R4hAsiV94t9ab08CzPbM1k5GoFw6neYrdUBdyV+2I9f3CXadMwgieebgxtKrs6XfR8xrA/Vb2c3duTURu2ekFV0wZ6Zd/7O6rmM8mPtwjy+5q1zLizKyoQi/OOTbCSVDQpP+5FQ/qEsPjSTzfw1fsiMA9zRHxA8YF6eOZSe1XkS8aZ1gzCzFwwYOdbr12KDHbVdvLi/V8cjgm2cIvYu+q54i6rGV0oHK52hxbBA8I7T0/66sWRFgV7NKFJ8/yPwM3nLkE2jPWt3strrOmCOCoC3d2RBA5ygcVZ7Zn7vuh0m2tps7rj/mO3HHpLgVEHoNsqQdySWTBd5GOjp9AaG8ZeInT4gYfUEQKmIlDFCJCZPOOd7apv6MipDUYOF3WWdrQRV8XiLYLeFnxLUrXOgNQMjpXAkrtTNqxArmcjEUJYFvfG4/sEA36R5T/avY8ao/5Lb8idXRKxhbpXtOEUfxxrqAM4HR0Zcz5kbLRDChYwi157+rS3njE6P8gED131F8ebNIGZ0u8OLaDpCbyGeKmPMgSXecNlZBlfCtfnJXgiyzTMJuB/zZaLvxMeBpk1fiVOdlJkYrJ6zyrXo9j7STS3nlUhjQKOdZEHRLfAHFq+ZRDVS92cpfxXPZ20fk+578HlygNVxXRFMImMZJL3k/mzJDFiTp3n7ybMU4lMuVql4ZOBdnBWAffMfX0rGk7qy7j8qsOqrpqF13lEjsP/zVoEvr4A5lgRSzpeu6CpzVqLxdZlQiNr8midcQf/rIjWGTA8/qtQ39xyXRnQM92IhvcQJWtJD7a/3lASeexuzW5XK/u/41IHmuaF7EREhg7xMdk05yNocy77If4HxjsFLXlMDwGbEJ2hnuLHDFrgo7wCkFxsD3tKLPnTFRNTyhEeY0nlj/6dTbD9yzO714uSP3a579EjS9a1bE4i4ZpIbi2/+tJ46vc4sISXZoeX1QFK82kxhGw00MkGHzmuLTn947i/26Vg1QAlMtzu/Lxv+ufNOg4GndhJr5c0fWZG+PSI7iXQB2/8ZgHfyZDHPmaichMM3mK3WeztzQrMX5l9k7cPff4lfjUbnkFFxJ5a4dM1urXAuChcNCiFTprDfOQhgoe0rykgP/JSXHEIv2JTKgJG306yEzrqztYrpdgBWoUPiJ5SafOGODHZRF4GJtb1EYOjywq1onsfoSpkYsvlWBahEAWgVbbZs0aQe5ti/Uow/cDGxeCSeOyss/suYlHyZ8trWSWNyhLdtqE6vycpAouq4QSg0M0lA2/kNVcYklmLzuOsoSxAZ X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2025 03:22:59.2265 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24b85be6-5619-4f10-501e-08dd95bb4a4c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6096 To simplify the mappings from global VCMDQs to VINTFs' LVCMDQs, the design chose to do static allocations and mappings in the global reset function. However, with the user-owned VINTF support, it exposes a security concern: if user space VM only wants one LVCMDQ for a VINTF, statically mapping two or more LVCMDQs creates a hidden VCMDQ that user space could DoS attack by writing random stuff to overwhelm the kernel with unhandleable IRQs. Thus, to support the user-owned VINTF feature, a LVCMDQ mapping has to be done dynamically. HW allows pre-assigning global VCMDQs in the CMDQ_ALLOC registers, without finalizing the mappings by keeping CMDQV_CMDQ_ALLOCATED=0. So, add a pair of map/unmap helper that simply sets/clears that bit. For kernel-owned VINTF0, move LVCMDQ mappings to tegra241_vintf_hw_init(), and the unmappings to tegra241_vintf_hw_deinit(). For user-owned VINTFs that will be added, the mappings/unmappings will be on demand upon an LVCMDQ allocation from the user space. However, the dynamic LVCMDQ mapping/unmapping can complicate the timing of calling tegra241_vcmdq_hw_init/deinit(), which write LVCMDQ address space, i.e. requiring LVCMDQ to be mapped. Highlight that with a note to the top of either of them. Acked-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 37 +++++++++++++++++-- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 8d418c131b1b..869c90b660c1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -351,6 +351,7 @@ tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, /* HW Reset Functions */ +/* This function is for LVCMDQ, so @vcmdq must not be unmapped yet */ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -379,6 +380,7 @@ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) dev_dbg(vcmdq->cmdqv->dev, "%sdeinited\n", h); } +/* This function is for LVCMDQ, so @vcmdq must be mapped prior */ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -404,16 +406,42 @@ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) return 0; } +/* Unmap a global VCMDQ from the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_unmap_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval & ~CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%sunmapped\n", h); +} + static void tegra241_vintf_hw_deinit(struct tegra241_vintf *vintf) { - u16 lidx; + u16 lidx = vintf->cmdqv->num_lvcmdqs_per_vintf; - for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) - if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) + /* HW requires to unmap LVCMDQs in descending order */ + while (lidx--) { + if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { tegra241_vcmdq_hw_deinit(vintf->lvcmdqs[lidx]); + tegra241_vcmdq_unmap_lvcmdq(vintf->lvcmdqs[lidx]); + } + } vintf_write_config(vintf, 0); } +/* Map a global VCMDQ to the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_map_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval | CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%smapped\n", h); +} + static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) { u32 regval; @@ -441,8 +469,10 @@ static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) */ vintf->hyp_own = !!(VINTF_HYP_OWN & readl(REG_VINTF(vintf, CONFIG))); + /* HW requires to map LVCMDQs in ascending order */ for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) { if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { + tegra241_vcmdq_map_lvcmdq(vintf->lvcmdqs[lidx]); ret = tegra241_vcmdq_hw_init(vintf->lvcmdqs[lidx]); if (ret) { tegra241_vintf_hw_deinit(vintf); @@ -476,7 +506,6 @@ static int tegra241_cmdqv_hw_reset(struct arm_smmu_device *smmu) for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) { regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, idx); regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, lidx); - regval |= CMDQV_CMDQ_ALLOCATED; writel_relaxed(regval, REG_CMDQV(cmdqv, CMDQ_ALLOC(qidx++))); }