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Thu, 1 May 2025 16:02:23 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 21/23] iommu/tegra241-cmdqv: Do not statically map LVCMDQs Date: Thu, 1 May 2025 16:01:27 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A346:EE_|MN2PR12MB4173:EE_ X-MS-Office365-Filtering-Correlation-Id: 97ee6425-b2f8-45d8-647d-08dd890446a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|82310400026|7416014|36860700013; X-Microsoft-Antispam-Message-Info: cP0LgRnkGTXgG+oJk1AH7lBOqvzc9LTI+QpTceBN/oDoNLtm1PJLsjQjY3xBFJH2Omepn/CxfrwV8mBQ3mi10c52EdqaK3lMVunUJ77E3406oeZI0Roa9N5xizVcQzD3PEEcMpNztobf0BPp7tLZNlIXqF5Pm6LRjP2EPdQZLM3fEEg4tSPTXcM4IUAsJRJH8rejkva18D1AgCjArPcTmsjIXr228Z7UZS0pSruXj5p1UHBaO/vdWnu3QjM17hOYpHNcu4dZm5EoQ0Z7tog5wYlG+bonz2DFKD94pB+Ja8xB5njNnoqxyx8j0DTY8YKQ+aotFsLiofQa53AZ7QEBJYD4jiEzHSFVq2FslM6ELgI8aTlcIQRuM16wcsJt7w3RF9ENjl3ts4KcfVTNj8oDp+E+ccbC13yOPT94XfBWFlzs9NsKXdJraWMfI7T3eSrqR8yNivjF1O6VSIZoMmZsrOl2r0avnFuRLtemCFZSpv7203m+p4ymea5VacQ4jG+01VufXjmbtYKt4FqRh+r4aod9VK7jpXU0Ctd1TZQeBw4jt0MvrCf52u0vChT6HD0jchTxWXUJBg/GVbab8ITq6Z93pBqlXQPQQFP/giqJyRQkNLvfqKJpDpTcYV/8r5sFnPX0nTq82nsrAATSfP2S0KRcRQ4p2mOuH2eMq+4DzC+YbSlAHywycO6nmAxC7NZH+M5j8qByH/pL9so4Q/VkMMPaKUnRbEAscw5WRgYU+e1xO2CgoBJJFx4yi1he7jQAZ7lcvLzZWzRMxsQtJJ9Vro0x4obOtY2Wz2yjCGnMTQSV/gSoY9LgP72owGfJjj/Gn26m0143TqU34geLqvu6jpYwc9hXntN9zOIvQrCFmVnrbTRG2g4xYo4Ds/NbfuoRtOuhXSJqPT5QswFNfQl9qViX4VYPwedKRLPMn3Gy/UzYHzPMP/S/FQ1km11iNrHuWxonNcjZy1Mz5MfvU4L/VgoRcCtVdZdwVOgqpxYU9ZFgBHMhTfwH+s2srsvAFG4PggGrIjXqjJ8+wobVZiW5KUi1Zu/ZYLi1bTjYYmXSLrTSVXnIjLD+80GnL+iOk7qS/rEoxu5Dud1JZS+yyjWiJq7P4weaPi4r6dBZf6NNRwohRIPPCdR6ru5wNBEgHktWN1Nrhb78so5PQtdIp/I9JQSfxs4Ak3wQ8hN5eF9uZEgmUKhVYRaGp6KbkPApre/kbLTX+6WzU/L9Uc3TDzkTSvQXzq0sl6h0UYD/I6Cz8WvEeRueAF67koohbGHb7PHvR4Dwf7dR3dIDEOyLoIl/Fh93LxNjuzfOGCmfCOsupGqxUSVdZ0g+PbL8xsjKAwBd/jyqfvaQfNfrAHGtXM52KcN0w/Xb9MGnleYfU7qXH8nfpuZw+1hUVkiKWYQQkxnR84qRtgIUCzRkPRSvcSY6ib6BmxIHUtFNBfrWmPKAtAhULsXuLrdBADGKz/qwt4cTcwLKh0AJCTFzlx4Mwki4x+3wo2NvSs/Z8xPx5+2hLWBNDctxOGh22Fqm/SfvmzuQ X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(82310400026)(7416014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2025 23:02:41.3144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97ee6425-b2f8-45d8-647d-08dd890446a5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A346.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4173 To simplify the mappings from global VCMDQs to VINTFs' LVCMDQs, the design chose to do static allocations and mappings in the global reset function. However, with the user-owned VINTF support, it exposes a security concern: if user space VM only wants one LVCMDQ for a VINTF, statically mapping two or more LVCMDQs creates a hidden VCMDQ that user space could DoS attack by writing random stuff to overwhelm the kernel with unhandleable IRQs. Thus, to support the user-owned VINTF feature, a LVCMDQ mapping has to be done dynamically. HW allows pre-assigning global VCMDQs in the CMDQ_ALLOC registers, without finalizing the mappings by keeping CMDQV_CMDQ_ALLOCATED=0. So, add a pair of map/unmap helper that simply sets/clears that bit. Delay the LVCMDQ mappings to tegra241_vintf_hw_init(), and the unmappings to tegra241_vintf_hw_deinit(). However, the dynamic LVCMDQ mapping/unmapping can complicate the timing of calling tegra241_vcmdq_hw_init/deinit(), which write LVCMDQ address space, i.e. requiring LVCMDQ to be mapped. Highlight that with a note to the top of either of them. Acked-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 37 +++++++++++++++++-- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 8d418c131b1b..869c90b660c1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -351,6 +351,7 @@ tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, /* HW Reset Functions */ +/* This function is for LVCMDQ, so @vcmdq must not be unmapped yet */ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -379,6 +380,7 @@ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) dev_dbg(vcmdq->cmdqv->dev, "%sdeinited\n", h); } +/* This function is for LVCMDQ, so @vcmdq must be mapped prior */ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -404,16 +406,42 @@ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) return 0; } +/* Unmap a global VCMDQ from the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_unmap_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval & ~CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%sunmapped\n", h); +} + static void tegra241_vintf_hw_deinit(struct tegra241_vintf *vintf) { - u16 lidx; + u16 lidx = vintf->cmdqv->num_lvcmdqs_per_vintf; - for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) - if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) + /* HW requires to unmap LVCMDQs in descending order */ + while (lidx--) { + if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { tegra241_vcmdq_hw_deinit(vintf->lvcmdqs[lidx]); + tegra241_vcmdq_unmap_lvcmdq(vintf->lvcmdqs[lidx]); + } + } vintf_write_config(vintf, 0); } +/* Map a global VCMDQ to the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_map_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval | CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%smapped\n", h); +} + static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) { u32 regval; @@ -441,8 +469,10 @@ static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) */ vintf->hyp_own = !!(VINTF_HYP_OWN & readl(REG_VINTF(vintf, CONFIG))); + /* HW requires to map LVCMDQs in ascending order */ for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) { if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { + tegra241_vcmdq_map_lvcmdq(vintf->lvcmdqs[lidx]); ret = tegra241_vcmdq_hw_init(vintf->lvcmdqs[lidx]); if (ret) { tegra241_vintf_hw_deinit(vintf); @@ -476,7 +506,6 @@ static int tegra241_cmdqv_hw_reset(struct arm_smmu_device *smmu) for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) { regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, idx); regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, lidx); - regval |= CMDQV_CMDQ_ALLOCATED; writel_relaxed(regval, REG_CMDQV(cmdqv, CMDQ_ALLOC(qidx++))); }