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Thu, 8 May 2025 20:03:37 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 18/23] iommu/arm-smmu-v3-iommufd: Support implementation-defined hw_info Date: Thu, 8 May 2025 20:02:39 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B5:EE_|IA0PR12MB8422:EE_ X-MS-Office365-Filtering-Correlation-Id: 54fed90b-a10a-41f3-6b72-08dd8ea61f3f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: 9qssmmD/13WjxIU7Ld0/rvOEVEALkr9fUlojmP9JBVqeBBk/ACn4QjKV+37yJ4Q3zVyCLwkLxbMtoVH68ZiSAz8quT5FYB9PZdk6Y79/Llrm76DIK4mcLZbIj7Gh/NYuO4buqIS7O9F57oVCVbCb2aFnPjoyOfDD/7rTnhvTSChSORVMivrrY6b7Nht4SavxW0QKtO8ONvDD68ctKPLrFVo69awPD/pAQmFRuBXroxmTcQ4ODG3e6PGyCujwBeJI6QsNKv4j8ShCBkcwyt3KwLES+tOqcCnq1bNQgK8gl7VBfI/boCKQGWNKCqTx0TfF4NlodOjIePTTnABRQKDZEGZQzJEb0S+4AwtWA8TX1XdVIDAR646tQTga6gSFnZMDy4ZBorb176mg7qZQ4s+Kn/Lx7xeVnisxkNaRsyNmuRRN4UOia1BOFiWRUTtom/5rMu9/wEHT1YlMj8W6AQED41dSj6isrdBnBJJLYdeygnrFi0uxSqHFgFi3GnMflBVD30I36qsNGVj8QbjOmwORnDdzWZ9gvix3qhcWBjT/FYlLGpCAJHbEBIK69FmFBiWHuhPBLwmqngmY1Hepm44WoWM345yMi/v0qk2Mv/bYAUD/lEDmIRV/vW80oBh7d4dGFVw6AKITk69LZsZEwXxKGhRXRGBWLJJMXneFPo0B/8KBurhH3eW+b3Lzq9jVIparRcTX2voU2rOeX9i11CkBKBu+KJ0hkAwJlIcBhY300BoFGV9oF+V0zHG1D4S2HMK5lsjP7F//4OlfUjrJ45qLCBxfd7XF9yJX+hrVwTqMzDSl/2yHFpMiGhPaevziYpLtJm1ZdVBG5dMO0PvRbCrBZStBSx171MDzg3xQa3Ub0QqV7KFOK/D41MNWUF7oeJ2uBTO++MNMIDcoFLDiVFCc28ZtMjO2ySGWb/mh2q8EljQY9pK6Ohm1S2g6fXpLD7somJawaEump5wxQFw6+dRSqEdCc0qANojvIIjarrxGOFAubSDcENfVoKFBKKna2D7S53ZVcAHcUe5g8HZvN0v3Dxuf9TuKzaJPtK4ojvGd+lpDepKCHzrndz1/QiaExjpet5t3aWwPLP4fmjtoZ+qs8QyvccP2wx+1XbDtu7hIyOYLnKJiZMEqyIBHarynRvclJKx/P5UOT5k0oWTk5/AljgdV/P2bHaw7A0D7sdt6NVwOws+hDCY+aU63uap5f+5EZDMDMQb7ScLufaJF29GDIMmnOCBiu85vqFiafULcFr3cooGMpZM135oRk3AHkKsrcDNdyShmfwDkh3HdI47cbCEaunXXo3n3MB7Za23h51gygan8CrgbbIK5uOkUSyS6kjo/YXMRGPDj7OrKxoVMsqjjR1D32xJYURkhyiiIHq73UVFRMttyzbqs/eqZaVSfnIH2JCaX6DRXsm1RJ7IqCggpVXFBqT65i2OmVr1ZQzyaK7Ua698MblCCKUghTh5L3Kr88Mvj/oXdIHGQDo7X9YscGIjF17zUYIbDQopHWLzSYPhwgdv/Sdr2aktNAaHV X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(82310400026)(7416014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2025 03:03:49.5154 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54fed90b-a10a-41f3-6b72-08dd8ea61f3f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8422 Repurpose the @__reserved field in the struct iommu_hw_info_arm_smmuv3, to an HW implementation-defined field @impl. This will be used by Tegra241 CMDQV implementation on top of a standard ARM SMMUv3 IOMMU. The @impl will be only valid if @flags is set with an implementation-defined flag. Thus in the driver-level, add an hw_info impl op that will return such a flag and fill the impl field. Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + include/uapi/linux/iommufd.h | 4 ++-- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 17 ++++++++++++++--- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index a5835af72417..bab7a9ce1283 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -726,6 +726,7 @@ struct arm_smmu_impl_ops { struct arm_smmu_domain *smmu_domain, struct iommufd_ctx *ictx, unsigned int viommu_type, const struct iommu_user_data *user_data); + u32 (*hw_info)(struct arm_smmu_device *smmu, u32 *impl); }; /* An SMMUv3 instance */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 001e2deb5a2d..28ab42a85268 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -554,7 +554,7 @@ struct iommu_hw_info_vtd { * (IOMMU_HW_INFO_TYPE_ARM_SMMUV3) * * @flags: Must be set to 0 - * @__reserved: Must be 0 + * @impl: Must be 0 * @idr: Implemented features for ARM SMMU Non-secure programming interface * @iidr: Information about the implementation and implementer of ARM SMMU, * and architecture version supported @@ -585,7 +585,7 @@ struct iommu_hw_info_vtd { */ struct iommu_hw_info_arm_smmuv3 { __u32 flags; - __u32 __reserved; + __u32 impl; __u32 idr[6]; __u32 iidr; __u32 aidr; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index b316d1df043f..8ea9a022e444 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -10,6 +10,7 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type) { struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_device *smmu = master->smmu; struct iommu_hw_info_arm_smmuv3 *info; u32 __iomem *base_idr; unsigned int i; @@ -18,15 +19,25 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type) if (!info) return ERR_PTR(-ENOMEM); - base_idr = master->smmu->base + ARM_SMMU_IDR0; + base_idr = smmu->base + ARM_SMMU_IDR0; for (i = 0; i <= 5; i++) info->idr[i] = readl_relaxed(base_idr + i); - info->iidr = readl_relaxed(master->smmu->base + ARM_SMMU_IIDR); - info->aidr = readl_relaxed(master->smmu->base + ARM_SMMU_AIDR); + info->iidr = readl_relaxed(smmu->base + ARM_SMMU_IIDR); + info->aidr = readl_relaxed(smmu->base + ARM_SMMU_AIDR); *length = sizeof(*info); *type = IOMMU_HW_INFO_TYPE_ARM_SMMUV3; + if (smmu->impl_ops && smmu->impl_ops->hw_info) { + u32 flags, impl; + + flags = smmu->impl_ops->hw_info(smmu, &impl); + if (flags) { + info->impl = impl; + info->flags |= flags; + } + } + return info; }