From patchwork Fri Apr 25 09:28:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason-JH Lin X-Patchwork-Id: 884681 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57AC522E3E3; Fri, 25 Apr 2025 09:32:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745573566; cv=none; b=pmPMsw2rqgowrk++m5OsKFLaxKNtHh46F2iZGOrUssiSkK52oc6toj40TCUv3MW7a5ehdDe8fXfWNwqWqnyLXH/47v6k+yVx5ZIb2GWU2ixRBjIa9XKti5b8qs1BhVr2jvujjbW8CbB21z4kEi91cSYp5Fq1OBrfHyzO4J3SZZg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745573566; c=relaxed/simple; bh=aYQMBNplTVaHyclpbyKpZ08KlElOEJt5FXn2y9TfiXg=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Jjry8mJGDyMRLNsXetHv/+4iOCK4EzcZ2dD7FNNumEyUZtd0663hbQG2lU+wXs4xZt9IQt9soec3J1hw8LNllGKuJA5r9q/uILAcGNkUMeY9kItlcgeg/Ite7xSUQSzY18zbhUOj5stz77a80rqN342sBVedwCPD/KCxw4M3T0I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=ULv/3UtO; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ULv/3UtO" X-UUID: 3acc597421b811f0980a8d1746092496-20250425 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=fUbJyBVUQ/Ent9qo9h24NLjKVtcs8TqR5cFHXMQPspI=; b=ULv/3UtOxoa2esyo19+2Zq17hCsdtVTMR+vG0MFGYLPKZj2PuOnM6gRkyHu/3fgkZsKOuWh9tar7kZM3oBRd8Vf4h3PFiH46YKAOj7vKfbFyMyaRpAGLgKPut7oBKwvyDUjTz2o//KB5fBuPp4qewNXxkEIgZyJhKrY3fICAnNA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:77041dac-c0d3-4b96-9c7d-4f8abc1f3ec1, IP:0, UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f, CLOUDID:5d1d9df0-ff26-40e8-a637-f0e9524b171a, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0|50,EDM:-3,IP:ni l,URL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 3acc597421b811f0980a8d1746092496-20250425 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1984012854; Fri, 25 Apr 2025 17:32:39 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 17:32:37 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 17:32:37 +0800 From: Jason-JH Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Mauro Carvalho Chehab CC: Matthias Brugger , Jason-JH Lin , Nancy Lin , Singo Chang , Paul-PL Chen , Moudy Ho , Xavier Chang , Xiandong Wang , Sirius Wang , Fei Shao , Chen-yu Tsai , , , , , , , Subject: [PATCH v5 00/19] Add GCE support for MT8196 Date: Fri, 25 Apr 2025 17:28:32 +0800 Message-ID: <20250425093237.1543918-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N This patch series adds support for the MediaTek MT8196 SoC in the CMDQ driver and related subsystems. The changes include adding compatible names and iommus property, updating driver data to accommodate hardware changes, and modifying the usage of CMDQ APIs to support non-subsys ID hardware. --- Change in v5: 1. Rebase on tag: next-20250424 + patch [1]. 2. Split adding driver data for MT8196 patch to 3 independent patch and add more detail commit message to each patch. 3. Refine passing shift_pa as the parameter in API to storing it into the cmdq_pkt. 4. Refine DMA address potential issue in cmdq mailbox driver. 5. Change the mminfra_offset related mbox API to passing it by cmdq_pkt. 6. Add new cmdq_pkt_write_pa() and cmdq_pkt_write_subsys() APIs to replace the cmdq_pkt_write(). [1] mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting - https://patchwork.kernel.org/project/linux-mediatek/patch/20250421035650.441383-1-jason-jh.lin@mediatek.com/ Change in v4: 1. Remove dt-binding header and add a gce header in dts folder. 2. Remove dot in sign-off name. 3. Change addr type from u32 to dma_addr_t for cmdq_reg_shift_addr() and cmdq_reg_revert_addr(). Change in v3: 1. Merge 2 dt-bindings pathes together and add more detail commit message. 2. Change type u32 to phys_addr_t for pa_base of struct cmdq_client_reg. 3. Remove cmdq_subsys_is_valid() and subsys_num in CMDQ driver. 4. Add CMDQ_SUBSYS_INVALID to check subsys instead of using cmdq_subsys_is_invalid(). 5. Make use of CMDQ_THR_SPR0 define to the parameter of CMDQ APIs. 6. Rebase on the new MACRO in mtk-mdp3-comp.h. Change in v2: 1. Remove the constant and fix warning in dt-bindings. 2. Remove the pa_base parameter of CMDQ APIs and related modification. 3. Move subsys checking to client drivers and use 2 alternative CMDQ APIs to achieve the same functionality. Jason-JH Lin (19): arm64: dts: mediatek: Add GCE header for MT8196 mailbox: mtk-cmdq: Refine DMA address handling for the command buffer mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating instruction soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create() soc: mediatek: mtk-cmdq: Add cmdq_pkt_jump_rel_temp() for removing shift_pa media: platform: mtk-mdp3: Change cmdq_pkt_jump_rel() to cmdq_pkt_jump_rel_temp() soc: mediatek: mtk-cmdq: Remove shift_pa parameter from cmdq_pkt_jump() media: platform: mtk-mdp3: Use cmdq_pkt_jump_rel() without shift_pa soc: mediatek: mtk-cmdq: Remove cmdq_pkt_jump() and cmdq_pkt_jump_rel_temp() mailbox: mtk-cmdq: Add GCE hardware virtualization configuration mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction mailbox: mtk-cmdq: Add driver data to support for MT8196 soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without subsys ID support soc: mediatek: mtk-cmdq: Add new APIs to replace cmdq_pkt_write() and cmdq_pkt_write_mask() soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses soc: mediatek: Add programming flow for unsupported subsys ID hardware drm/mediatek: Add programming flow for unsupported subsys ID hardware media: mediatek: mdp3: Add programming flow for unsupported subsys ID hardware soc: mediatek: mtk-cmdq: Remove cmdq_pkt_write() and cmdq_pkt_write_mask() arch/arm64/boot/dts/mediatek/mt8196-gce.h | 612 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 +- drivers/mailbox/mtk-cmdq-mailbox.c | 115 +++- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 16 +- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 70 +- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 2 - .../platform/mediatek/mdp3/mtk-mdp3-core.h | 1 - drivers/soc/mediatek/mtk-cmdq-helper.c | 68 +- drivers/soc/mediatek/mtk-mmsys.c | 12 +- drivers/soc/mediatek/mtk-mutex.c | 8 +- include/linux/mailbox/mtk-cmdq-mailbox.h | 19 +- include/linux/soc/mediatek/mtk-cmdq.h | 83 ++- 12 files changed, 941 insertions(+), 89 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-gce.h