From patchwork Mon Feb 22 12:24:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 386463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 641CEC433E9 for ; Mon, 22 Feb 2021 12:27:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1CB5C64E2F for ; Mon, 22 Feb 2021 12:27:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230437AbhBVM0E (ORCPT ); Mon, 22 Feb 2021 07:26:04 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:57662 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230351AbhBVMZM (ORCPT ); Mon, 22 Feb 2021 07:25:12 -0500 Received: from localhost.localdomain (unknown [IPv6:2a01:e0a:4cb:a870:5956:412c:4850:9073]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id A7FE71F44FF7; Mon, 22 Feb 2021 12:24:21 +0000 (GMT) From: Benjamin Gaignard To: ezequiel@collabora.com, p.zabel@pengutronix.de, mchehab@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, gregkh@linuxfoundation.org, mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, jernej.skrabec@siol.net, peng.fan@nxp.com, hverkuil-cisco@xs4all.nl, dan.carpenter@oracle.com Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v3 4/9] media: uapi: Add a control for HANTRO driver Date: Mon, 22 Feb 2021 13:24:01 +0100 Message-Id: <20210222122406.41782-5-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210222122406.41782-1-benjamin.gaignard@collabora.com> References: <20210222122406.41782-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The HEVC HANTRO driver needs to know the number of bits to skip at the beginning of the slice header. That is a hardware specific requirement so create a dedicated control that this purpose. Signed-off-by: Benjamin Gaignard --- version 3: - Fix typo in field name include/uapi/linux/hantro-v4l2-controls.h | 20 ++++++++++++++++++++ include/uapi/linux/v4l2-controls.h | 5 +++++ 2 files changed, 25 insertions(+) create mode 100644 include/uapi/linux/hantro-v4l2-controls.h diff --git a/include/uapi/linux/hantro-v4l2-controls.h b/include/uapi/linux/hantro-v4l2-controls.h new file mode 100644 index 000000000000..a8dfd6b1a2a9 --- /dev/null +++ b/include/uapi/linux/hantro-v4l2-controls.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#ifndef __UAPI_HANTRO_V4L2_CONYTROLS_H__ +#define __UAPI_HANTRO_V4L2_CONYTROLS_H__ + +#include +#include + +#define V4L2_CID_HANTRO_HEVC_EXTRA_DECODE_PARAMS (V4L2_CID_USER_HANTRO_BASE + 0) + +/** + * struct hantro_hevc_extra_decode_params - extra decode parameters for hantro driver + * @hevc_hdr_skip_length: header first bits offset + */ +struct hantro_hevc_extra_decode_params { + __u32 hevc_hdr_skip_length; + __u8 padding[4]; +}; + +#endif diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index 039c0d7add1b..ced7486c7f46 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -209,6 +209,11 @@ enum v4l2_colorfx { * We reserve 128 controls for this driver. */ #define V4L2_CID_USER_CCS_BASE (V4L2_CID_USER_BASE + 0x10f0) +/* + * The base for HANTRO driver controls. + * We reserve 32 controls for this driver. + */ +#define V4L2_CID_USER_HANTRO_BASE (V4L2_CID_USER_BASE + 0x1170) /* MPEG-class control IDs */ /* The MPEG controls are applicable to all codec controls