From patchwork Wed Mar 31 17:35:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Velikov X-Patchwork-Id: 413196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C96AEC4363F for ; Wed, 31 Mar 2021 17:36:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E2CF61090 for ; Wed, 31 Mar 2021 17:36:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234580AbhCaRf4 (ORCPT ); Wed, 31 Mar 2021 13:35:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234471AbhCaRfi (ORCPT ); Wed, 31 Mar 2021 13:35:38 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F727C061574; Wed, 31 Mar 2021 10:35:38 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id j4-20020a05600c4104b029010c62bc1e20so1551905wmi.3; Wed, 31 Mar 2021 10:35:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mAneJlrkY4/IZLQNpt5ahOvEPFy19jWwGdcAjZr3nhE=; b=YmtZQ+LunBSbH82nppx0e1AHv/erPdAV4rYhHMfTZm5/5CB1E3qrRmqrE980tmzGNR wXzZjOHx2GUc+HKIElUWHVymFNmLAIF6i+kNbkOVhrYDrfmgoOwl8N99OtJg1/Y9Q8pu Tr8+IwMJudTRE3xQE+6S9s+psA2EwSL5m4CKNXrvZde05MYUxqbE7wO3Otlz0aXn43OV 6tmMHep/dQZs8QfM+1Vc7j4vl9uVo4Gio2lCukWS1FcBezTZ5SUm8dqQ5xbdyMOSVWIo 6JtQsaIMJO9CF5yWEaeWuiy92EivH7uyscpg4VxO5AKTPwlURVKbnDJF4XDa9Og89ZJu WSrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mAneJlrkY4/IZLQNpt5ahOvEPFy19jWwGdcAjZr3nhE=; b=sbjwVxPAsgUwQ3lsknX5jlCqzUIuaR5pnP4BOKsulzndp2Xq3gnm/iG0qk15DzoylX y1SvQU0hMnrCYxURdb/apN0rP1YN4+bSUXXjkMA1JflqWoAmG28OCF8E2S4JV9UY8kqp L06IVoS3T2EQWbac2qsLtGUNuE+yihPKawf0Dqpxhqrs3B7qeVXRFtEtdqLn8Vak/1Cx 7HGapwN3dzAEu1YB3dcGPbTANFT0RTaFPVbz51b9el9ejw9ooPj6sHJoEs/bLpaxShZ/ lO/ZXW2q67n5Ub4GqJPq3DcNrMSxQiDazFLk31dWc2r2jsqosfkR2cmZJ2pMtDkbDvDJ udOw== X-Gm-Message-State: AOAM533RRnLUeRw8Leh8Nw1wploV03YwMzBwrk6JlGnzu0sJ8rgdSDq7 0CRO+e6CkcD1XiKCMO564v0= X-Google-Smtp-Source: ABdhPJzlxACnhIRQ+AXKJJI1GcyjjGziE0R7NWal5rREJt1JXk2twRrZNDdgHHf0WjBbeLi2WZFJSw== X-Received: by 2002:a05:600c:22cd:: with SMTP id 13mr4137385wmg.90.1617212137004; Wed, 31 Mar 2021 10:35:37 -0700 (PDT) Received: from arch-x1c3.. ([2a00:5f00:102:0:6e1d:cfb9:fb12:552d]) by smtp.gmail.com with ESMTPSA id 12sm4714200wmw.43.2021.03.31.10.35.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 10:35:36 -0700 (PDT) From: Emil Velikov To: kernel@collabora.com, Ezequiel Garcia , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org Cc: emil.l.velikov@gmail.com, Frank Rowand Subject: [PATCH v3 8/9] media: hantro: add initial SAMA5D4 support Date: Wed, 31 Mar 2021 18:35:19 +0100 Message-Id: <20210331173520.184191-9-emil.l.velikov@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210331173520.184191-1-emil.l.velikov@gmail.com> References: <20210331173520.184191-1-emil.l.velikov@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Emil Velikov The SoC features a Hantro G1 compatible video decoder, supporting the MPEG-2, VP8 and H264 codecs with resolutions up-to 1280x720. Post-processing core is also available on the SoC. Cc: Rob Herring Cc: Frank Rowand Cc: devicetree@vger.kernel.org> Acked-by: Nicolas Ferre Reviewed-by: Ezequiel Garcia Signed-off-by: Emil Velikov --- v2 - Split DT and defconfig changes to separate patches (Eze) - s/Atmel/Microchip/ (Nicolas) v3 - Drop the clk/irq names (RobH) --- drivers/staging/media/hantro/Kconfig | 10 +- drivers/staging/media/hantro/Makefile | 3 + drivers/staging/media/hantro/hantro_drv.c | 3 + drivers/staging/media/hantro/hantro_hw.h | 1 + .../staging/media/hantro/sama5d4_vdec_hw.c | 117 ++++++++++++++++++ 5 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/media/hantro/sama5d4_vdec_hw.c diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig index 5b6cf9f62b1a..20b1f6d7b69c 100644 --- a/drivers/staging/media/hantro/Kconfig +++ b/drivers/staging/media/hantro/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config VIDEO_HANTRO tristate "Hantro VPU driver" - depends on ARCH_MXC || ARCH_ROCKCHIP || COMPILE_TEST + depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || COMPILE_TEST depends on VIDEO_DEV && VIDEO_V4L2 select MEDIA_CONTROLLER select MEDIA_CONTROLLER_REQUEST_API @@ -24,6 +24,14 @@ config VIDEO_HANTRO_IMX8M help Enable support for i.MX8M SoCs. +config VIDEO_HANTRO_SAMA5D4 + bool "Hantro VDEC SAMA5D4 support" + depends on VIDEO_HANTRO + depends on ARCH_AT91 || COMPILE_TEST + default y + help + Enable support for Microchip SAMA5D4 SoCs. + config VIDEO_HANTRO_ROCKCHIP bool "Hantro VPU Rockchip support" depends on VIDEO_HANTRO diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile index 3747a32799b2..f4b99901eeee 100644 --- a/drivers/staging/media/hantro/Makefile +++ b/drivers/staging/media/hantro/Makefile @@ -22,6 +22,9 @@ hantro-vpu-y += \ hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \ imx8m_vpu_hw.o +hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \ + sama5d4_vdec_hw.o + hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \ rk3288_vpu_hw.o \ rk3399_vpu_hw.o diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index d1294eb9cd07..74a3d9eab454 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -478,6 +478,9 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, +#endif +#ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 + { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index 73c71bb2320c..4d39da1d1581 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -152,6 +152,7 @@ extern const struct hantro_variant rk3399_vpu_variant; extern const struct hantro_variant rk3328_vpu_variant; extern const struct hantro_variant rk3288_vpu_variant; extern const struct hantro_variant imx8mq_vpu_variant; +extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_postproc_regs hantro_g1_postproc_regs; diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c new file mode 100644 index 000000000000..d52ac626f98a --- /dev/null +++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hantro VDEC driver + * + * Copyright (C) 2021 Collabora Ltd, Emil Velikov + */ + +#include "hantro.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt sama5d4_vdec_postproc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .codec_mode = HANTRO_MODE_NONE, + }, +}; + +static const struct hantro_fmt sama5d4_vdec_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + }, + { + .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, + .codec_mode = HANTRO_MODE_MPEG2_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1280, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 720, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_VP8_FRAME, + .codec_mode = HANTRO_MODE_VP8_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1280, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 720, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1280, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 720, + .step_height = MB_DIM, + }, + }, +}; + +static int sama5d4_hw_init(struct hantro_dev *vpu) +{ + return 0; +} + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops sama5d4_vdec_codec_ops[] = { + [HANTRO_MODE_MPEG2_DEC] = { + .run = hantro_g1_mpeg2_dec_run, + .reset = hantro_g1_reset, + .init = hantro_mpeg2_dec_init, + .exit = hantro_mpeg2_dec_exit, + }, + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .reset = hantro_g1_reset, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .reset = hantro_g1_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + +static const struct hantro_irq sama5d4_irqs[] = { + { NULL, hantro_g1_irq }, +}; + +static const char * const sama5d4_clk_names[] = { NULL }; + +const struct hantro_variant sama5d4_vdec_variant = { + .dec_fmts = sama5d4_vdec_fmts, + .num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts), + .postproc_fmts = sama5d4_vdec_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts), + .postproc_regs = &hantro_g1_postproc_regs, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = sama5d4_vdec_codec_ops, + .init = sama5d4_hw_init, + .irqs = sama5d4_irqs, + .num_irqs = ARRAY_SIZE(sama5d4_irqs), + .clk_names = sama5d4_clk_names, + .num_clocks = ARRAY_SIZE(sama5d4_clk_names), +};