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From: Pratyush Yadav
To: Maxime Ripard ,
Mauro Carvalho Chehab ,
Rob Herring , Pratyush Yadav ,
Kishon Vijay Abraham I , Vinod Koul ,
Peter Ujfalusi ,
Steve Longerbeam ,
Benoit Parrot , ,
, ,
,
CC: Vignesh Raghavendra ,
Tomi Valkeinen ,
Chunfeng Yun ,
Laurent Pinchart
Subject: [PATCH v2 09/18] media: cadence: csi2rx: Fix stream data configuration
Date: Wed, 26 May 2021 20:52:59 +0530
Message-ID: <20210526152308.16525-10-p.yadav@ti.com>
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Firstly, there is no VC_EN bit present in the STREAM_DATA_CFG register.
Bit 31 is part of the VL_SELECT field. Remove it completely.
Secondly, it makes little sense to enable ith virtual channel for ith
stream. Sure, there might be a use-case that demands it. But there might
also be a use case that demands all streams to use the 0th virtual
channel. Prefer this case over the former because it is less arbitrary
and also makes it very clear what the limitations of the current driver
is instead of giving a false impression that multiple virtual channels
are supported.
Signed-off-by: Pratyush Yadav
---
(no changes since v1)
drivers/media/platform/cadence/cdns-csi2rx.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c
index ecc43a618c34..1df21f462f3c 100644
--- a/drivers/media/platform/cadence/cdns-csi2rx.c
+++ b/drivers/media/platform/cadence/cdns-csi2rx.c
@@ -48,7 +48,6 @@
#define CSI2RX_STREAM_STATUS_RDY BIT(31)
#define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008)
-#define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31)
#define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16)
#define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c)
@@ -301,8 +300,11 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx)
writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
csi2rx->base + CSI2RX_STREAM_CFG_REG(i));
- writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT |
- CSI2RX_STREAM_DATA_CFG_VC_SELECT(i),
+ /*
+ * Enable one virtual channel. When multiple virtual channels
+ * are supported this will have to be changed.
+ */
+ writel(CSI2RX_STREAM_DATA_CFG_VC_SELECT(0),
csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i));
writel(CSI2RX_STREAM_CTRL_START,