From patchwork Thu Dec 23 19:16:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 527860 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE00BC433FE for ; Thu, 23 Dec 2021 19:16:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350001AbhLWTQr (ORCPT ); Thu, 23 Dec 2021 14:16:47 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:48584 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349984AbhLWTQq (ORCPT ); Thu, 23 Dec 2021 14:16:46 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1BNJGfdt031738; Thu, 23 Dec 2021 13:16:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1640287001; bh=UOBoBf5jPZmq44GOkxtvSQRyD77EhLUs4Xa2ASMj/QI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IrLNwhyEpfSX8nToCy2oSsmwhwDRZw8DFM2g2w5HTKQXOxjNKIvq7w7azHAL6Cay2 eBQTPPEQ4jYsrnjSkqNfPg2s9cwFy8AjKHcrZfTTQwiLp3kRL/sqM5lE34Vh44+E3p UbnuWRCZ5VkQ3eewBQLrfiS1vB4utSoyNkO3ePUo= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1BNJGfdC124494 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 23 Dec 2021 13:16:41 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 23 Dec 2021 13:16:40 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 23 Dec 2021 13:16:40 -0600 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BNJGGQS006164; Thu, 23 Dec 2021 13:16:37 -0600 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlun?= =?utf-8?q?d?= , , , Subject: [PATCH v5 05/14] media: cadence: csi2rx: Soft reset the streams before starting capture Date: Fri, 24 Dec 2021 00:46:06 +0530 Message-ID: <20211223191615.17803-6-p.yadav@ti.com> X-Mailer: git-send-email 2.33.1.835.ge9e5ba39a7 In-Reply-To: <20211223191615.17803-1-p.yadav@ti.com> References: <20211223191615.17803-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This resets the stream state machines and FIFOs, giving them a clean slate. On J721E if the streams are not reset before starting the capture, the captured frame gets wrapped around vertically on every run after the first. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- Changes in v5: - Make i unsigned. - Add Laurent's R-by. drivers/media/platform/cadence/cdns-csi2rx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index afd4a0da8235..baf8ec649a25 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -39,6 +39,7 @@ #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) #define CSI2RX_STREAM_CTRL_START BIT(0) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) @@ -135,12 +136,22 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) static void csi2rx_reset(struct csi2rx_priv *csi2rx) { + unsigned int i; + writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, csi2rx->base + CSI2RX_SOFT_RESET_REG); udelay(10); writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + + /* Reset individual streams. */ + for (i = 0; i < csi2rx->max_streams; i++) { + writel(CSI2RX_STREAM_CTRL_SOFT_RST, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + usleep_range(10, 20); + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } } static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx)