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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id bg19sm1915252wmb.47.2022.01.11.04.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jan 2022 04:50:11 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, mchehab@kernel.org, hverkuil@xs4all.nl, robert.foss@linaro.org Cc: jonathan@marek.ca, andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, jgrahsl@snap.com, hfink@snap.com, vladimir.zapolskiy@linaro.org, dmitry.baryshkov@linaro.org, bryan.odonoghue@linaro.org Subject: [PATCH v3 8/8] media: camss: Point sm8250 at the correct vdda regulators Date: Tue, 11 Jan 2022 12:52:12 +0000 Message-Id: <20220111125212.2343184-9-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220111125212.2343184-1-bryan.odonoghue@linaro.org> References: <20220111125212.2343184-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Reviewing the RB5 schematic its clear that we have missed out on defining both of the power-rails associated with the CSI PHY. Other PHYs such as the UFS, PCIe and USB connect to these rails and define each regulator individually. This means if we were to switch off the other various PHYs which enable these rails, the CAMSS would not appropriately power-on the CSI PHY. Reviewed-by: Robert Foss Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 859b397912cc8..a2f97311f7606 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -723,7 +723,7 @@ static const struct resources csiphy_res_8250[] = { static const struct resources csid_res_8250[] = { /* CSID0 */ { - .regulators = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -735,7 +735,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID1 */ { - .regulators = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -747,7 +747,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID2 */ { - .regulators = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -758,7 +758,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID3 */ { - .regulators = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, .clock_rate = { { 400000000 }, { 400000000 },