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Mon, 11 Apr 2022 06:51:07 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org Cc: hverkuil-cisco@xs4all.nl, robh+dt@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v20] arm64: dts: freescale: imx8q: add imx vpu codec entries Date: Mon, 11 Apr 2022 14:50:49 +0800 Message-Id: <20220411065049.13188-1-ming.qian@nxp.com> X-Mailer: git-send-email 2.35.1 X-ClientProxiedBy: SG2P153CA0040.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::9) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 56f25a51-c32a-4783-d53d-08da1b87a748 X-MS-TrafficTypeDiagnostic: AM9PR04MB8306:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: j/9L9/bDeYMEMQgzzmARHoPS55VGnt3b6RZZQSyohsgYuoIQJUusncKrhf6u713t5nI0QwQ80VYAV0AvxqX6bsmfJ5n6mPI9W+B+ySXdpR8zqFiiyhAaQ8X0R/4XhCo+Tk2Q+qC3IV0bc1tOczWUy3ELX9I5uG7AG0p/vGqplgbzajRHtPiq7n2vwbtMMjI4ARqN1hTyMKeLJK4PKAK8SZ8m6Ns00broHKDJQ/c3wYaFwAVHeJx0g3+1mnvMZJmZCHSbpQ1voa7dwEJgv+/GhNsX9ouj3iiYrHOWtokJ6cL/glXd7GATrbv1wBKVpfJnv9TLCF4gzNxX06WcaX6nfC4Y7Hi4dELtb8naMhHAKJoJc0Yv6sJg2EYa1jUPLeRUS1DKds30VbVmiFaDo9DVaM+rDbBztZWUETnuKnwEdu+KXV6J7GxzF60snW0gk+cGcOkP1g06IYG132ZIWhokTS8xWC4rKwtGTnnjupdwav+riCmXXGL8ushBQPa0PoC5SGbxcpEM4HB0pKPleNYL4REeStxDHJlNcuksfImHJ7AK4lmmonswavbl4BHKzdr/wztvpq1o9R3dH+X5ljsCZ7oIpZxEnoz6rVc0AsVs4YuRfN8lwn6xpDMSsLSfIeoacKTnmeu1dwXL+bD/WJwPYdjCjgjMxyL8ix2qEP9cZx4gmaPhZG3XrAxTi6+JTpliX3ReZE+uYa3i6u5iNwz7JheXeMIM6IBPcKD4mvnYCTuw9H8g2kBeaOmqrL1Kj3rRqnRGHmmVhmhwyTN1WuDJDg== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 74 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 25 +++++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 24 ++++++ 3 files changed, 123 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file mode 100644 index 000000000000..c6540768bdb9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Dong Aisheng + */ + +vpu: vpu@2c000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + reg = <0 0x2c000000 0 0x1000000>; + power-domains = <&pd IMX_SC_R_VPU>; + status = "disabled"; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + status = "disabled"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + status = "disabled"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + status = "disabled"; + }; + + vpu_core0: vpu-core@2d080000 { + reg = <0x2d080000 0x10000>; + compatible = "nxp,imx8q-vpu-decoder"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + status = "disabled"; + }; + + vpu_core1: vpu-core@2d090000 { + reg = <0x2d090000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + status = "disabled"; + }; + + vpu_core2: vpu-core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 863232a47004..07d8dd8160f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -135,6 +135,14 @@ &lpuart0 { status = "okay"; }; +&mu_m0 { + status = "okay"; +}; + +&mu1_m0 { + status = "okay"; +}; + &scu_key { status = "okay"; }; @@ -196,6 +204,23 @@ &usdhc2 { status = "okay"; }; +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d040000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index dbec7c106e0b..a79ae33cbad2 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -46,6 +46,9 @@ aliases { serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + vpu_core0 = &vpu_core0; + vpu_core1 = &vpu_core1; + vpu_core2 = &vpu_core2; }; cpus { @@ -162,10 +165,30 @@ reserved-memory { #size-cells = <2>; ranges; + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; }; + + encoder_rpc: encoder-rpc@94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; + }; }; pmu { @@ -287,6 +310,7 @@ map0 { /* sorted in register address */ #include "imx8-ss-img.dtsi" + #include "imx8-ss-vpu.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi"