From patchwork Tue Jan 31 13:03:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 650789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C6D3C636D7 for ; Tue, 31 Jan 2023 13:03:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231765AbjAaNDu (ORCPT ); Tue, 31 Jan 2023 08:03:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231634AbjAaNDr (ORCPT ); Tue, 31 Jan 2023 08:03:47 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7EDCC153; Tue, 31 Jan 2023 05:03:44 -0800 (PST) Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:d507:461a:a036:bf89]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6974F6602EDB; Tue, 31 Jan 2023 13:03:43 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675170223; bh=xFuGtGTNupLtCWrqn28rJaQua02Q5BjDoZkdnX0clbQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Oaho7Cieo4djYgupJKPfUiikKJSOUIOU1kPjNMtjN6kO7edRWD4fCCvB+WJPlPqUX 6gl2F/Dtn+V62BFk3iBXWSKR0bHMC97CupGtzIio137tWWPrgh/DdWz9Qea0bU/TmG aSmTQrpLGzMm5ZIjZhdfdsOeXn+DzIOgx1rtacGKdu2wLFZTNAXUlXdSvY8ZtDf/xz CTY6FT2TiOO9gqPg7BbEljWxAx484RdHtN7F7SibZG27qIERisUKV39e02APFs7O7u epatNpsOfFfC3up1byRBakq/WKeSCx4nsYIeBKoeOHFKR8YuiwRG+l3aLhA72yl5Bp cgYNqj0VmM7ww== From: Benjamin Gaignard To: ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de, mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, hverkuil-cisco@xs4all.nl, nicolas.dufresne@collabora.co.uk Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v7 3/5] media: verisilicon: Do not set ctx->bit_depth in hantro_try_ctrl() Date: Tue, 31 Jan 2023 14:03:25 +0100 Message-Id: <20230131130327.776899-4-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230131130327.776899-1-benjamin.gaignard@collabora.com> References: <20230131130327.776899-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org In hantro_try_ctrl() we should only check the values inside control parameters and not set ctx->bit_depth. That must be done in controls set function. Create a set control function for hevc where ctx->bit_depth is set at the right time. Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") Signed-off-by: Benjamin Gaignard --- version 7: - Remove unused ctx variable in hantro_try_ctrl(). .../media/platform/verisilicon/hantro_drv.c | 32 ++++++++++++++----- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 8cb4a68c9119..6d8bc55ea627 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -251,11 +251,6 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) { - struct hantro_ctx *ctx; - - ctx = container_of(ctrl->handler, - struct hantro_ctx, ctrl_handler); - if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; @@ -274,8 +269,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) /* Only 8-bit and 10-bit are supported */ return -EINVAL; - - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; @@ -324,6 +317,24 @@ static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl) return 0; } +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hantro_ctx *ctx; + + ctx = container_of(ctrl->handler, + struct hantro_ctx, ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_STATELESS_HEVC_SPS: + ctx->bit_depth = ctrl->p_new.p_hevc_sps->bit_depth_luma_minus8 + 8; + break; + default: + return -EINVAL; + } + + return 0; +} + static const struct v4l2_ctrl_ops hantro_ctrl_ops = { .try_ctrl = hantro_try_ctrl, }; @@ -336,6 +347,11 @@ static const struct v4l2_ctrl_ops hantro_vp9_ctrl_ops = { .s_ctrl = hantro_vp9_s_ctrl, }; +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { + .try_ctrl = hantro_try_ctrl, + .s_ctrl = hantro_hevc_s_ctrl, +}; + #define HANTRO_JPEG_ACTIVE_MARKERS (V4L2_JPEG_ACTIVE_MARKER_APP0 | \ V4L2_JPEG_ACTIVE_MARKER_COM | \ V4L2_JPEG_ACTIVE_MARKER_DQT | \ @@ -470,7 +486,7 @@ static const struct hantro_ctrl controls[] = { .codec = HANTRO_HEVC_DECODER, .cfg = { .id = V4L2_CID_STATELESS_HEVC_SPS, - .ops = &hantro_ctrl_ops, + .ops = &hantro_hevc_ctrl_ops, }, }, { .codec = HANTRO_HEVC_DECODER,