diff --git a/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,dwc-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 MIPI CSI-2 Host Controller receiver
+
+maintainers:
+  - G.N. Zhou <guoniu.zhou@nxp.com>
+
+description: |-
+  The MIPI CSI-2 receiver found on i.MX93 originates from Synopsys
+  DesignWare Core and it implements the CSI-2 protocol on the host
+  side and a DPHY configured as a Slave acts as the physical layer.
+  Two data lanes are supported on i.MX93 family devices and the data
+  rate of each lane support up to 1.5Gbps.
+
+  While the CSI-2 receiver is separate from the MIPI D-PHY IP core,
+  the PHY is completely wrapped by the CSI-2 controller and expose
+  a control interface which only can communicate with CSI-2 controller
+  This binding thus covers both IP cores.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx93-mipi-csi2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: The peripheral clock (a.k.a. APB clock)
+      - description: The pixel clock
+      - description: The MIPI D-PHY clock
+
+  clock-names:
+    items:
+      - const: per
+      - const: pixel
+      - const: phy_cfg
+
+  power-domains:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port node, single endpoint describing the CSI-2 transmitter.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                items:
+                  - const: 1
+                  - const: 2
+
+              fsl,hsfreqrange:
+                $ref: /schemas/types.yaml#/definitions/uint32
+                description:
+                  Used to select the desired high speed frequency range
+                  according to data lane bit rate. Please refer to i.MX93
+                  reference manual MIPI CSI-2 DPHY chapter to get a valid
+                  value.
+
+            required:
+              - data-lanes
+              - fsl,hsfreqrange
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port node
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx93-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/power/fsl,imx93-power.h>
+
+    mipi-csi@4ae00000 {
+        compatible = "fsl,imx93-mipi-csi2";
+        reg = <0x4ae00000 0x10000>;
+        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clks IMX93_CLK_MIPI_CSI_GATE>,
+                 <&clks IMX93_CLK_CAM_PIX>,
+                 <&clks IMX93_CLK_MIPI_PHY_CFG>;
+        clock-names = "per", "pixel", "phy_cfg";
+        power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                mipi_from_sensor: endpoint {
+                    remote-endpoint = <&ap1302_to_mipi>;
+                    data-lanes = <1 2>;
+                    fsl,hsfreqrange = <0x2c>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                mipi_to_isi: endpoint {
+                    remote-endpoint = <&isi_in>;
+                };
+            };
+        };
+    };
+...
