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It also has the option to bypass the PLL and use EXTCLK directly as SYSCLK. The current driver implementation uses a hardcoded PLL configuration that requires a specific EXTCLK frequency. Depending on the available clocks, it can be desirable to use a different PLL configuration or to bypass it. Read the property 'bypass-pll' from the DT in mt9m114_parse_dt(). Depending on this value, write the correct PLL register values and calculate the correct pixel clock value. Signed-off-by: Mathis Foerst --- drivers/media/i2c/mt9m114.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/media/i2c/mt9m114.c b/drivers/media/i2c/mt9m114.c index fa64d6d315a1..edbc0447141d 100644 --- a/drivers/media/i2c/mt9m114.c +++ b/drivers/media/i2c/mt9m114.c @@ -261,6 +261,7 @@ #define MT9M114_CAM_PGA_PGA_CONTROL CCI_REG16(0xc95e) #define MT9M114_CAM_SYSCTL_PLL_ENABLE CCI_REG8(0xc97e) #define MT9M114_CAM_SYSCTL_PLL_ENABLE_VALUE BIT(0) +#define MT9M114_CAM_SYSCTL_PLL_DISABLE_VALUE 0x00 #define MT9M114_CAM_SYSCTL_PLL_DIVIDER_M_N CCI_REG16(0xc980) #define MT9M114_CAM_SYSCTL_PLL_DIVIDER_VALUE(m, n) (((n) << 8) | (m)) #define MT9M114_CAM_SYSCTL_PLL_DIVIDER_P CCI_REG16(0xc982) @@ -377,6 +378,7 @@ struct mt9m114 { struct gpio_desc *reset; struct regulator_bulk_data supplies[3]; struct v4l2_fwnode_endpoint bus_cfg; + bool bypass_pll; struct { unsigned int m; @@ -743,14 +745,20 @@ static int mt9m114_initialize(struct mt9m114 *sensor) } /* Configure the PLL. */ - cci_write(sensor->regmap, MT9M114_CAM_SYSCTL_PLL_ENABLE, - MT9M114_CAM_SYSCTL_PLL_ENABLE_VALUE, &ret); - cci_write(sensor->regmap, MT9M114_CAM_SYSCTL_PLL_DIVIDER_M_N, - MT9M114_CAM_SYSCTL_PLL_DIVIDER_VALUE(sensor->pll.m, - sensor->pll.n), - &ret); - cci_write(sensor->regmap, MT9M114_CAM_SYSCTL_PLL_DIVIDER_P, - MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(sensor->pll.p), &ret); + if (sensor->bypass_pll) { + cci_write(sensor->regmap, MT9M114_CAM_SYSCTL_PLL_ENABLE, + MT9M114_CAM_SYSCTL_PLL_DISABLE_VALUE, &ret); + } else { + cci_write(sensor->regmap, MT9M114_CAM_SYSCTL_PLL_ENABLE, + MT9M114_CAM_SYSCTL_PLL_ENABLE_VALUE, &ret); + cci_write(sensor->regmap, MT9M114_CAM_SYSCTL_PLL_DIVIDER_M_N, + MT9M114_CAM_SYSCTL_PLL_DIVIDER_VALUE(sensor->pll.m, + sensor->pll.n), + &ret); + cci_write(sensor->regmap, MT9M114_CAM_SYSCTL_PLL_DIVIDER_P, + MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(sensor->pll.p), + &ret); + } cci_write(sensor->regmap, MT9M114_CAM_SENSOR_CFG_PIXCLK, sensor->pixrate, &ret); @@ -2268,8 +2276,12 @@ static int mt9m114_clk_init(struct mt9m114 *sensor) * for 16-bit per pixel, transmitted in DDR over a single lane. For * parallel mode, the sensor ouputs one pixel in two PIXCLK cycles. */ - sensor->pixrate = clk_get_rate(sensor->clk) * sensor->pll.m + if (sensor->bypass_pll) { + sensor->pixrate = clk_get_rate(sensor->clk) / 2; + } else { + sensor->pixrate = clk_get_rate(sensor->clk) * sensor->pll.m / ((sensor->pll.n + 1) * (sensor->pll.p + 1)); + } link_freq = sensor->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY ? sensor->pixrate * 8 : sensor->pixrate * 2; @@ -2321,6 +2333,7 @@ static int mt9m114_parse_dt(struct mt9m114 *sensor) { struct fwnode_handle *fwnode = dev_fwnode(&sensor->client->dev); struct fwnode_handle *ep; + struct device_node *dev_node = sensor->client->dev.of_node; int ret; ep = fwnode_graph_get_next_endpoint(fwnode, NULL); @@ -2349,6 +2362,8 @@ static int mt9m114_parse_dt(struct mt9m114 *sensor) goto error; } + sensor->bypass_pll = of_property_read_bool(dev_node, "bypass-pll"); + return 0; error: