From patchwork Sat May 10 07:53:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 889107 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 420EF1EA7D2; Sat, 10 May 2025 07:58:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746863909; cv=none; b=qZysEVDOv/J/AaSt5KCQGAgkcfGM+SERRXXgndyh3t/O+ON64/BsVH8gv5F1A1CpvYZoQvF8n0A7yslZb5I6CFtId/XsUaa1kJsRf7pg6vBlQnYGeIehG44KNKaVjFVDvCBCgOzP/HOKivd47hho1otxr+Qck5aXUcg5fy039Wo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746863909; c=relaxed/simple; bh=BQZBuAj+vNPkAYjt2/16DRoGHNnOcDHMeLYU4/V0PfM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UIkg6Ngp5FIBO/z0huOkpZ/5k81pZGSJcCQPxx1PgRCu/0WAsL56UnohHk+vd1EYpH+tkaWBsqGvIrCIYQEyeOAVVZKBuS84H9hZmjsj1LZ8IXI01mPHWG98NqG4fFV6LXP3JM03/G66c5FBtdhhZjeichGh7ZEf1re+pbnBqNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=h6N6ko3v; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="h6N6ko3v" X-UUID: 8ce4f00a2d7411f0813e4fe1310efc19-20250510 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=gADYw74csEBUNnKaQWCDgsGf/Crg494yQ5XTZTHGL40=; b=h6N6ko3vzy1UK17x7bqU91O9WdqP+DZ6oCnLlWgKi7VXk4ybSw7ul/BN6S4LgJgC3ymdn/d7i+8d63B5y+kTmPydwzPzR1uncc0iLTDEzFLtzEmH0UpxW9tcLmPMLmp2gCZ5l1iykgaCl5y38TfkrT5hso8FUmJAClHoDt4PxZ4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:fee376f1-bdbd-47a1-aaed-e335027f7480, IP:0, UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f, CLOUDID:980dcee0-512b-41ef-ab70-9303a9a81417, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 8ce4f00a2d7411f0813e4fe1310efc19-20250510 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1014924433; Sat, 10 May 2025 15:58:25 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Sat, 10 May 2025 15:58:22 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Sat, 10 May 2025 15:58:21 +0800 From: Yunfei Dong To: =?utf-8?q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , Sebastian Fricke , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert , Daniel Almeida CC: Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , Yunfei Dong , , , , , , Subject: [PATCH 07/14] media: mediatek: vcodec: define MT8196 vcodec levels. Date: Sat, 10 May 2025 15:53:37 +0800 Message-ID: <20250510075357.11761-8-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com> References: <20250510075357.11761-1-yunfei.dong@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The supported level and profile are not the same for different codecs and architecture. Select the correct one. Signed-off-by: Yunfei Dong --- .../mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index d873159b9b30..c1cef78471a9 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -555,6 +555,7 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2; break; case MTK_VDEC_MT8195: + case MTK_VDEC_MT8196: cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0; break; case MTK_VDEC_MT8183: @@ -573,6 +574,7 @@ static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg, switch (ctx->dev->chip_name) { case MTK_VDEC_MT8188: case MTK_VDEC_MT8195: + case MTK_VDEC_MT8196: cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; break; default: @@ -589,6 +591,7 @@ static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; break; case MTK_VDEC_MT8195: + case MTK_VDEC_MT8196: cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; break; default: @@ -603,6 +606,7 @@ static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, switch (ctx->dev->chip_name) { case MTK_VDEC_MT8188: case MTK_VDEC_MT8195: + case MTK_VDEC_MT8196: cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; break; default: @@ -620,6 +624,7 @@ static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; break; case MTK_VDEC_MT8195: + case MTK_VDEC_MT8196: cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; break; case MTK_VDEC_MT8186: @@ -637,6 +642,7 @@ static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, switch (ctx->dev->chip_name) { case MTK_VDEC_MT8188: case MTK_VDEC_MT8195: + case MTK_VDEC_MT8196: cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2; break; default: