| Message ID | 20230410184526.15990-1-blarson@amd.com |
|---|---|
| Headers | show |
| Series | Support AMD Pensando Elba SoC | expand |
On Mon, 10 Apr 2023 at 20:47, Brad Larson <blarson@amd.com> wrote: > > SoCs with device specific Cadence implementation, such as setting > byte-enables before the write, need to override writel(). Add a > callback where the default is writel() for all existing chips. > > Signed-off-by: Brad Larson <blarson@amd.com> > Acked-by: Adrian Hunter <adrian.hunter@intel.com> Applied for next, thanks! Kind regards Uffe > --- > > v10 changes: > - The 1st patch adding private writel() is unchanged. The 2nd patch is split > into two patches to provide for device specific init in one patch with no > effect on existing designs. Then add the pensando support into the next patch. > Then the 4th patch is mmc hardware reset support which is unchanged. > > v9 changes: > - No change to this patch but as some patches are deleted and this is > a respin the three successive patches to sdhci-cadence.c are > patches 12, 13, and 14 which do the following: > > 1. Add ability for Cadence specific design to have priv writel(). > 2. Add Elba SoC support that requires its own priv writel() for > byte-lane control . > 3. Add support for mmc hardware reset. > > --- > drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++----- > 1 file changed, 13 insertions(+), 5 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c > index 6f2de54a5987..708d4297f241 100644 > --- a/drivers/mmc/host/sdhci-cadence.c > +++ b/drivers/mmc/host/sdhci-cadence.c > @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param { > struct sdhci_cdns_priv { > void __iomem *hrs_addr; > bool enhanced_strobe; > + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); > unsigned int nr_phy_params; > struct sdhci_cdns_phy_param phy_params[]; > }; > @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { > { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, > }; > > +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, > + void __iomem *reg) > +{ > + writel(val, reg); > +} > + > static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, > u8 addr, u8 data) > { > @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, > > tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | > FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); > - writel(tmp, reg); > + priv->priv_writel(priv, tmp, reg); > > tmp |= SDHCI_CDNS_HRS04_WR; > - writel(tmp, reg); > + priv->priv_writel(priv, tmp, reg); > > ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); > if (ret) > return ret; > > tmp &= ~SDHCI_CDNS_HRS04_WR; > - writel(tmp, reg); > + priv->priv_writel(priv, tmp, reg); > > ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), > 0, 10); > @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) > tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); > tmp &= ~SDHCI_CDNS_HRS06_MODE; > tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); > - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); > + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); > } > > static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) > @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) > */ > for (i = 0; i < 2; i++) { > tmp |= SDHCI_CDNS_HRS06_TUNE_UP; > - writel(tmp, reg); > + priv->priv_writel(priv, tmp, reg); > > ret = readl_poll_timeout(reg, tmp, > !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), > @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev) > priv->nr_phy_params = nr_phy_params; > priv->hrs_addr = host->ioaddr; > priv->enhanced_strobe = false; > + priv->priv_writel = cdns_writel; > host->ioaddr += SDHCI_CDNS_SRS_BASE; > host->mmc_host_ops.hs400_enhanced_strobe = > sdhci_cdns_hs400_enhanced_strobe; > -- > 2.17.1 >
On Mon, 10 Apr 2023 at 20:47, Brad Larson <blarson@amd.com> wrote: > > Add support for AMD Pensando Elba SoC which explicitly > controls byte-lane enables on writes. > > Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which > allows Elba SoC sdhci_elba_ops to overwrite the SDHCI > IO memory accessors > > Signed-off-by: Brad Larson <blarson@amd.com> > Acked-by: Adrian Hunter <adrian.hunter@intel.com> Applied for next, thanks! Kind regards Uffe > --- > > v13 changes: > - Use GENMASK(7, 3) in elba_priv_writel() to set all byte enables > - Add a variable 'shift' with GENMASK(1, 0) in elba_write_w() and > elba_write_b() to set the byte enable variable. > > v11 changes: > - Remove elba-drv_init() call to platform_get_resource() since that > check is done inside devm_platform_ioremap_resource() > - Move spin_lock_init() before error check > - Remove extra parentheses > > v10 changes: > - Add Elba specific support into this 3rd patch. This builds on the private > writel() enabled in patch 1 followed by platform specific init() in patch 2. > - Specify when first used the reason for the spinlock use to order byte-enable > prior to write data. > > --- > drivers/mmc/host/Kconfig | 1 + > drivers/mmc/host/sdhci-cadence.c | 98 ++++++++++++++++++++++++++++++++ > 2 files changed, 99 insertions(+) > > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig > index 4745fe217ade..9f793892123c 100644 > --- a/drivers/mmc/host/Kconfig > +++ b/drivers/mmc/host/Kconfig > @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE > tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" > depends on MMC_SDHCI_PLTFM > depends on OF > + select MMC_SDHCI_IO_ACCESSORS > help > This selects the Cadence SD/SDIO/eMMC driver. > > diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c > index c528a25f48b8..5d1e9cef74f5 100644 > --- a/drivers/mmc/host/sdhci-cadence.c > +++ b/drivers/mmc/host/sdhci-cadence.c > @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { > > struct sdhci_cdns_priv { > void __iomem *hrs_addr; > + void __iomem *ctl_addr; /* write control */ > + spinlock_t wrlock; /* write lock */ > bool enhanced_strobe; > void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); > unsigned int nr_phy_params; > @@ -321,6 +323,91 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, > sdhci_set_uhs_signaling(host, timing); > } > > +/* Elba control register bits [6:3] are byte-lane enables */ > +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) > + > +/* > + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes > + * which includes writes to the HRS registers. The write lock (wrlock) > + * is used to ensure byte-lane enable, using write control (ctl_addr), > + * occurs before the data write. > + */ > +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, > + void __iomem *reg) > +{ > + unsigned long flags; > + > + spin_lock_irqsave(&priv->wrlock, flags); > + writel(GENMASK(7, 3), priv->ctl_addr); > + writel(val, reg); > + spin_unlock_irqrestore(&priv->wrlock, flags); > +} > + > +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) > +{ > + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); > +} > + > +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) > +{ > + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); > + u32 shift = reg & GENMASK(1, 0); > + unsigned long flags; > + u32 byte_enables; > + > + byte_enables = GENMASK(1, 0) << shift; > + spin_lock_irqsave(&priv->wrlock, flags); > + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); > + writew(val, host->ioaddr + reg); > + spin_unlock_irqrestore(&priv->wrlock, flags); > +} > + > +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) > +{ > + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); > + u32 shift = reg & GENMASK(1, 0); > + unsigned long flags; > + u32 byte_enables; > + > + byte_enables = BIT(0) << shift; > + spin_lock_irqsave(&priv->wrlock, flags); > + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); > + writeb(val, host->ioaddr + reg); > + spin_unlock_irqrestore(&priv->wrlock, flags); > +} > + > +static const struct sdhci_ops sdhci_elba_ops = { > + .write_l = elba_write_l, > + .write_w = elba_write_w, > + .write_b = elba_write_b, > + .set_clock = sdhci_set_clock, > + .get_timeout_clock = sdhci_cdns_get_timeout_clock, > + .set_bus_width = sdhci_set_bus_width, > + .reset = sdhci_reset, > + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, > +}; > + > +static int elba_drv_init(struct platform_device *pdev) > +{ > + struct sdhci_host *host = platform_get_drvdata(pdev); > + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); > + void __iomem *ioaddr; > + > + host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA; > + spin_lock_init(&priv->wrlock); > + > + /* Byte-lane control register */ > + ioaddr = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(ioaddr)) > + return PTR_ERR(ioaddr); > + > + priv->ctl_addr = ioaddr; > + priv->priv_writel = elba_priv_writel; > + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); > + > + return 0; > +} > + > static const struct sdhci_ops sdhci_cdns_ops = { > .set_clock = sdhci_set_clock, > .get_timeout_clock = sdhci_cdns_get_timeout_clock, > @@ -337,6 +424,13 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { > }, > }; > > +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { > + .init = elba_drv_init, > + .pltfm_data = { > + .ops = &sdhci_elba_ops, > + }, > +}; > + > static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { > .pltfm_data = { > .ops = &sdhci_cdns_ops, > @@ -477,6 +571,10 @@ static const struct of_device_id sdhci_cdns_match[] = { > .compatible = "socionext,uniphier-sd4hc", > .data = &sdhci_cdns_uniphier_drv_data, > }, > + { > + .compatible = "amd,pensando-elba-sd4hc", > + .data = &sdhci_elba_drv_data, > + }, > { .compatible = "cdns,sd4hc" }, > { /* sentinel */ } > }; > -- > 2.17.1 >
On Mon, Apr 10, 2023 at 11:45:14AM -0700, Brad Larson wrote: > Document the cadence qspi controller compatible for AMD Pensando > Elba SoC boards. The Elba qspi fifo size is 1024. This does not apply against current code, please check and resend.
On Mon, 10 Apr 2023 11:45:11 -0700, Brad Larson wrote: > This series enables support for AMD Pensando Elba SoC based platforms. > > The Elba SoC has the following features: > - Sixteen ARM64 A72 cores > - Dual DDR 4/5 memory controllers > - 32 lanes of PCIe Gen3/4 to the Host > - Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and > also a single 1GE management port. > - Storage/crypto offloads and 144 programmable P4 cores. > - QSPI and EMMC for SoC storage > - Two SPI interfaces for peripheral management > - I2C bus for platform management > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [03/15] dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC (no commit info) [04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller commit: 6282a6ceef62f5732082f691de8f82fcd49d4fb4 [09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC (no commit info) [10/15] spi: dw: Add support for AMD Pensando Elba SoC commit: 2c8606040a808aa01d2d9e4f5b9332e87bb66377 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
This series enables support for AMD Pensando Elba SoC based platforms. The Elba SoC has the following features: - Sixteen ARM64 A72 cores - Dual DDR 4/5 memory controllers - 32 lanes of PCIe Gen3/4 to the Host - Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and also a single 1GE management port. - Storage/crypto offloads and 144 programmable P4 cores. - QSPI and EMMC for SoC storage - Two SPI interfaces for peripheral management - I2C bus for platform management == V13 changes == v13-0013-mmc-sdhci-cadence-Add-AMD-Pensando-Elba-SoC-supp - Use GENMASK(7, 3) in elba_priv_writel() to set all byte enables - Add a variable 'shift' with GENMASK(1, 0) in elba_write_w() and elba_write_b() to set the byte enable variable. v13-0015-soc-amd-Add-support-for-AMD-Pensando-SoC-Control - Update include list in pensando-ctrl.c - Change variable spi_dev to spi throughout - Removed unneeded variable initialization, simplification of error checks, remove extra castings, and use dev_err_probe() - Sort the includes in amd-pensando-ctrl.h - Updates to cleanup if there is an error in penctrl_spi_probe() == V12 changes == v12-0004-dt-bindings-spi-dw-Add-AMD-Pensando-Elba-SoC-SPI - Correct property amd,pensando-elba-syscon description v12-0010-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC - Add a newline in function dw_spi_elba_init() v12-0015-soc-amd-Add-support-for-AMD-Pensando-SoC-Control - Fix gcc-12.1.0 warning: == V11 changes == v11-0002-dt-bindings-mmc-cdns-Add-AMD-Pensando-Elba-SoC - Remove resets description and reset-names - Add descriptions for amd,pensando-elba-sd4hc reg items v11-0003-dt-bindings-spi-cdns-Add-compatible-for-AMD-Pens - Removed redundant if/then for amd,pensando-elba-qspi v11-0005-dt-bindings-soc-amd-amd-pensando-elba-ctrl-Add-P - Fixed the compatible which should have stayed as 'amd,pensando-elba-ctrl', the commit message, and the filename. - Reference spi-peripheral-props - Delete spi-max-frequency - Remove num-cs from example v11-0008-arm64-dts-Add-AMD-Pensando-Elba-SoC-support - Delete reset-names - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' v11-0010-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC - Simplify dw_spi_elb_init by using syscon_regmap_lookup_by_phandle() v11-0013-mmc-sdhci-cadence-Add-AMD-Pensando-Elba-SoC-supp - Remove elba-drv_init() call to platform_get_resource() since that check is done inside devm_platform_ioremap_resource() - Move spin_lock_init() before error check - Remove extra parentheses v11-0015-soc-amd-Add-support-for-AMD-Pensando-SoC-Control - Fix the compatible to be specific 'amd,pensando-elba-ctrl' - Cast arguments flagged with a gcc-12.1.0 warning: Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202303061526.I8VPcR1M-lkp@intel.com/ == V10 changes == Binding property amd,pensando-elba-syscon was merged in 6.2 v10-0002-dt-bindings-mmc-cdns-Add-AMD-Pensando-Elba-SoC - Move reset-names property definition next to existing resets prop - Move allOf to the bottom and set resets/reset-names required only for pensando - Fix reg maxItems for existing, must be 1 v10-0003-dt-bindings-spi-cdns-Add-compatible-for-AMD-Pens - Fix cdns,fifo-depth, only amd,pensando-elba-qspi is 1024 bytes v10-0004-dt-bindings-spi-dw-Add-AMD-Pensando-Elba-SoC-SPI - Move definition of amd,pensando-elba-syscon into properties with a better description - Add amd,pensando-elba-syscon: false for non elba designs v10-0005-dt-bindings-soc-amd-amd-pensando-elbasr-Add-AMD- - Property renamed to amd,pensando-ctrl - Driver is renamed and moved to soc/drivers/amd affecting binding - Delete cs property, driver handles device node creation from parent num-cs fixing schema reg error in a different way v10-0010-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC - Delete struct dw_spi_elba, use regmap directly in priv v10-0011-mmc-sdhci-cadence-Enable-device-specific-overrid - The 1st patch adding private writel() is unchanged. The 2nd patch is split into two patches to provide for device specific init in one patch with no effect on existing designs. Then add the pensando support into the next patch. Then the 4th patch is mmc hardware reset support which is unchanged. v10-0012-mmc-sdhci-cadence-Support-device-specific-init-i - New patch to provide for platform specific init() with no change to existing designs. v10-0013-mmc-sdhci-cadence-Add-AMD-Pensando-Elba-SoC-supp - Add Elba specific support into this 3rd patch. This builds on the private writel() enabled in patch 1 followed by platform specific init() in patch 2. - Specify when first used the reason for the spinlock use to order byte-enable prior to write data. v10-0015-soc-amd-Add-support-for-AMD-Pensando-SoC-Control - Different driver implementation specific to this Pensando controller device. - Moved to soc/amd directory under new name based on guidance. This driver is of no use to any design other than all Pensando SoC based cards. - Removed use of builtin_driver, can be built as a module. == V9 changes == v9-0002-dt-bindings-mmc-cdns-Add-AMD-Pensando-Elba-SoC - Add reset-names and resets properties - Add if/then on property amd,pensando-elba-sd4hc to set reg property values for minItems and maxItems v9-0003-dt-bindings-spi-cdns-Add-compatible-for-AMD-Pensa - Add 1024 to cdns,fifo-depth property to resolve dtbs_check error v9-0004-dt-bindings-spi-dw-Add-AMD-Pensando-Elba-SoC-SPI- - Define property amd,pensando-elba-syscon - Move compatible amd,pensando-elba-spi ahead of baikal,bt1-ssi v9-0006-dt-bindings-mfd-amd-pensando-elbasr-Add-AMD-Pensa - Instead of four nodes, one per chip-select, a single node is used with reset-cells in the parent. - No MFD API is used anymore in the driver so it made sense to move this to drivers/spi. - This driver is common for all Pensando SoC based designs so changed the name to pensando-sr.c to not make it Elba SoC specific. - Added property cs for the chip-select number which is used by the driver to create /dev/pensr0.<cs> v9-0009-arm64-dts-Add-AMD-Pensando-Elba-SoC-support - Single node for spi0 system-controller and squash the reset-controller child into parent v9-0010-spi-cadence-quadspi-Add-compatible-for-AMD-Pensan - Rebase to linux-next 6.2.0-rc1 v9-0011-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC - Add use of macros GENMASK() and BIT() - Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET() v9-0012-mmc-sdhci-cadence-Enable-device-specific-override - No change to this patch but as some patches are deleted and this is a respin the three successive patches to sdhci-cadence.c are patches 12, 13, and 14 which do the following: 1. Add ability for Cadence specific design to have priv writel(). 2. Add Elba SoC support that requires its own priv writel() for byte-lane control . 3. Add support for mmc hardware reset. v9-0014-mmc-sdhci-cadence-Support-mmc-hardware-reset - Previously patch 17/17 - Changed delay after reset_control_assert() from 9 to 3 usec - Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset() v9-0015-spi-pensando-sr-Add-AMD-Pensando-SoC-System-Resou - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO == V6 changes == - Updated copyright and SPDX v6-0001-dt-bindings-arm-add-AMD-Pensando-boards - Delete 'Device Tree Bindings' in title v6-0002-dt-bindings-mmc-cdns-Add-AMD-Pensando-Elba-SoC - Change if/then for Elba which has a second reg for byte-lane control v6-0003-dt-bindings-spi-cdns-Add-compatible-for-AMD-Pensa - no change v6-0004-dt-bindings-spi-dw-Add-AMD-Pensando-Elba-SoC-SPI- - Add amd,pensando-elba-syscon v6-0005-dt-bindings-mfd-syscon-Add-amd-pensando-elba-sysc - no change v6-0006-dt-bindings-mfd-amd-pensando-elbasr-Add-AMD-Pensa - Expand description, rename nodes and change compatible usage v6-0007-dt-bindings-reset-amd-pensando-elbasr-reset-Add-A - Delete nodename pattern and changed spi0 to spi - File amd,pensando-elba-reset.h is deleted as there is only one reset used. - Update example v6-0008-MAINTAINERS-Add-entry-for-AMD-PENSANDO - no change v6-0009-arm64-Add-config-for-AMD-Pensando-SoC-platforms - no change v6-0010-arm64-dts-Add-AMD-Pensando-Elba-SoC-support - Update node names and add amd,pensando-elba-syscon - Delete use of amd,pensando-elba-reset.h which had a single definition v6-0011-spi-cadence-quadspi-Add-compatible-for-AMD-Pensan - Remove (void) cast v6-0012-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC - Update use of amd,pensando-elba-syscon v6-0013-mmc-sdhci-cadence-Enable-device-specific-override - Change this patch to add a priv_writel() callback where all existing designs use writel(). This separates the Elba support into three patches. The second patch is added to the end of the sequence for Elba support. The third patch enables mmc hardware reset. v6-0014-mfd-pensando-elbasr-Add-AMD-Pensando-Elba-System- - Updates from review comments - Use spi_message_init_with_transfers instead of init/add_tail API v6-0015-reset-elbasr-Add-AMD-Pensando-Elba-SR-Reset-Contr - Remove use of amd,pensando-elba-reset.h and use BIT() v6-0016-mmc-sdhci-cadence-Add-AMD-Pensando-Elba-SoC-suppo - Elba sdhci-cadence.c support added in this patch to build on 0013 which just adds a callback to override priv_writel() v6-0017-mmc-sdhci-cadence-Support-mmc-hardware-reset - New patch where Elba has a reset-controller for mmc hardware reset. The reset is implemented by a register in the cpld. == V5 changes == - Change to AMD Pensando instead of Pensando. - No reference to spidev in the device tree. Add multi-function driver pensando-elbasr and sub-device reset-elbasr which provides mfd and /dev interface to the cpld. - Rebase to linux-next tag next-20220609 5.19.0-rc1 - Redo the email list after rebase and using scripts/get_maintainer.pl == V4 changes == The version of dtschema used is 2022.3.2. v4-0001-dt-bindings-arm-add-Pensando-boards.patch - Add description and board compatible v4-0003-dt-bindings-mmc-Add-Pensando-Elba-SoC-binding.patch - Change from elba-emmc to elba-sd4hc to match file convention - Use minItems: 1 and maxItems: 2 to pass schema check v4-0005-dt-bindings-spi-dw-Add-Pensando-Elba-SoC-SPI-Control.patch - Add required property pensando,syscon-spics to go with pensando,elba-spi v4-0006-MAINTAINERS-Add-entry-for-PENSANDO.patch - Change Maintained to Supported v4-0007-arm64-Add-config-for-Pensando-SoC-platforms.patch - Fix a typo on interface max speed v4-0008-spi-cadence-quadspi-Add-compatible-for-Pensando-Elba.patch - Update due to spi-cadence-quadspi.c changes v4-0009-mmc-sdhci-cadence-Add-Pensando-Elba-SoC-support.patch - Change from elba-emmc to elba-sd4hc to match file convention v4-0010-spi-dw-Add-support-for-Pensando-Elba-SoC.patch - Use more descriptive dt property pensando,syscon-spics - Minor changes from review input v4-0011-arm64-dts-Add-Pensando-Elba-SoC-support.patch - Changed to dual copyright (GPL-2.0+ OR MIT) - Minor changes from review input == V3 changes == v3-0001-gpio-Add-Elba-SoC-gpio-driver-for-spi-cs-control.patch - This patch is deleted. Elba SOC specific gpio spics control is integrated into spi-dw-mmio.c. v3-0002-spi-cadence-quadspi-Add-QSPI-support-for-Pensando-El.patch - Changed compatible to "pensando,elba-qspi" to be more descriptive in spi-cadence-quadspi.c. - Arnd wondered if moving to DT properties for quirks may be the way to go. Feedback I've received on other patches was don't mix two efforts in one patch so I'm currently just adding the Elba support to the current design. v3-0003-spi-dw-Add-support-for-Pensando-Elba-SoC-SPI.patch - Changed the implementation to use existing dw_spi_set_cs() and integrated Elba specific CS control into spi-dw-mmio.c. The native designware support is for two chip-selects while Elba provides 4 chip-selects. Instead of adding a new file for this support in gpio-elba-spics.c the support is in one file (spi-dw-mmio.c). v3-0004-spidev-Add-Pensando-CPLD-compatible.patch - This patch is deleted. The addition of compatible "pensando,cpld" to spidev.c is not added and an existing compatible is used in the device tree to enable. v3-0005-mmc-sdhci-cadence-Add-Pensando-Elba-SoC-support.patch - Ulf and Yamada-san agreed the amount of code for this support is not enough to need a new file. The support is added into sdhci-cadence.c and new files sdhci-cadence-elba.c and sdhci-cadence.h are deleted. - Redundant defines are removed (e.g. use SDHCI_CDNS_HRS04 and remove SDIO_REG_HRS4). - Removed phy init function sd4_set_dlyvr() and used existing sdhci_cdns_phy_init(). Init values are from DT properties. - Replace devm_ioremap_resource(&pdev->dev, iomem) with devm_platform_ioremap_resource(pdev, 1) - Refactored the elba priv_writ_l() and elba_write_l() to remove a little redundant code. - The config option CONFIG_MMC_SDHCI_CADENCE_ELBA goes away. - Only C syntax and Elba functions are prefixed with elba_ v3-0006-arm64-Add-config-for-Pensando-SoC-platforms.patch - Added a little more info to the platform help text to assist users to decide on including platform support or not. v3-0007-arm64-dts-Add-Pensando-Elba-SoC-support.patch - Node names changed to DT generic names - Changed from using 'spi@' which is reserved - The elba-flash-parts.dtsi is kept separate as it is included in multiple dts files. - SPDX license tags at the top of each file - The compatible = "pensando,elba" and 'model' are now together in the board file. - UIO nodes removed - Ordered nodes by increasing unit address - Removed an unreferenced container node. - Dropped deprecated 'device_type' for uart0 node. v3-0010-dt-bindings-spi-cadence-qspi-Add-support-for-Pensand.patch - Updated since the latest documentation has been converted to yaml v3-0011-dt-bindings-gpio-Add-Pensando-Elba-SoC-support.patch - This patch is deleted since the Elba gpio spics is added to the spi dw driver and documented there. Because of the deletion of patches and merging of code the new patchset is not similar. A changelog is added into the patches for merged code to be helpful on the history. == V2 changes == - 01 Fix typo, return code value and log message. - 03 Remove else clause, intrinsic DW chip-select is never used. - 08-11 Split out dts and bindings to sub-patches - 10 Converted existing cadence-quadspi.txt to YAML schema - 13 New driver should use <linux/gpio/driver.h> Brad Larson (15): dt-bindings: arm: add AMD Pensando boards dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller MAINTAINERS: Add entry for AMD PENSANDO arm64: Add config for AMD Pensando SoC platforms arm64: dts: Add AMD Pensando Elba SoC support spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC spi: dw: Add support for AMD Pensando Elba SoC mmc: sdhci-cadence: Enable device specific override of writel() mmc: sdhci-cadence: Support device specific init during probe mmc: sdhci-cadence: Add AMD Pensando Elba SoC support mmc: sdhci-cadence: Support mmc hardware reset soc: amd: Add support for AMD Pensando SoC Controller .../devicetree/bindings/arm/amd,pensando.yaml | 26 ++ .../devicetree/bindings/mmc/cdns,sdhci.yaml | 27 +- .../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++ .../bindings/spi/cdns,qspi-nor.yaml | 19 +- .../bindings/spi/snps,dw-apb-ssi.yaml | 19 + MAINTAINERS | 9 + arch/arm64/Kconfig.platforms | 12 + arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 ++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 +++++ arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++ drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 175 +++++++- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/amd/Kconfig | 16 + drivers/soc/amd/Makefile | 2 + drivers/soc/amd/pensando-ctrl.c | 373 ++++++++++++++++++ drivers/spi/spi-cadence-quadspi.c | 19 + drivers/spi/spi-dw-mmio.c | 58 +++ include/uapi/linux/amd-pensando-ctrl.h | 30 ++ 23 files changed, 1421 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi create mode 100644 drivers/soc/amd/Kconfig create mode 100644 drivers/soc/amd/Makefile create mode 100644 drivers/soc/amd/pensando-ctrl.c create mode 100644 include/uapi/linux/amd-pensando-ctrl.h base-commit: fe15c26ee26efa11741a7b632e9f23b01aca4cc6