| Message ID | 20241101-imx-emmc-reset-v3-0-184965eed476@solid-run.com |
|---|---|
| Headers | show |
| Series | mmc: host: sdhci-esdhc-imx: implement emmc hardware reset | expand |
On 1/11/24 13:42, Josua Mayer wrote: > Signed-off-by: Josua Mayer <josua@solid-run.com> > --- > Changes in v3: > - reused existing control register definition from sdhci-esdhc.h > (Reported-by: Bough Chen <haibo.chen@nxp.com>) > - placed both control register mask definitions next to each other > - fixed timeout write register name > - Link to v2: https://lore.kernel.org/r/20241030-imx-emmc-reset-v2-0-b3a823393974@solid-run.com > > Changes in v2: > - replaced udelay with usleep_range > (Reported-by: Adrian Hunter <adrian.hunter@intel.com>) > - added comments for delay values > (Reported-by: Peng Fan <peng.fan@nxp.com>) > - delay values based on JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, > on page 159 > (Thanks to Bough Chen <haibo.chen@nxp.com>) > - added a second patch demonstrating a cosmetic issue revealed by first > patch - it bothered me during development but is not important > - Link to v1: https://lore.kernel.org/r/20241027-imx-emmc-reset-v1-1-d5d0c672864a@solid-run.com > > --- > Josua Mayer (2): > mmc: host: sdhci-esdhc-imx: implement emmc hardware reset > mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask For both: Acked-by: Adrian Hunter <adrian.hunter@intel.com>
On Fri, 1 Nov 2024 at 12:42, Josua Mayer <josua@solid-run.com> wrote: > > Signed-off-by: Josua Mayer <josua@solid-run.com> > --- > Changes in v3: > - reused existing control register definition from sdhci-esdhc.h > (Reported-by: Bough Chen <haibo.chen@nxp.com>) > - placed both control register mask definitions next to each other > - fixed timeout write register name > - Link to v2: https://lore.kernel.org/r/20241030-imx-emmc-reset-v2-0-b3a823393974@solid-run.com > > Changes in v2: > - replaced udelay with usleep_range > (Reported-by: Adrian Hunter <adrian.hunter@intel.com>) > - added comments for delay values > (Reported-by: Peng Fan <peng.fan@nxp.com>) > - delay values based on JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, > on page 159 > (Thanks to Bough Chen <haibo.chen@nxp.com>) > - added a second patch demonstrating a cosmetic issue revealed by first > patch - it bothered me during development but is not important > - Link to v1: https://lore.kernel.org/r/20241027-imx-emmc-reset-v1-1-d5d0c672864a@solid-run.com > > --- > Josua Mayer (2): > mmc: host: sdhci-esdhc-imx: implement emmc hardware reset > mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask > > drivers/mmc/host/sdhci-esdhc-imx.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) The series applied for next, thanks! Kind regards Uffe
Signed-off-by: Josua Mayer <josua@solid-run.com> --- Changes in v3: - reused existing control register definition from sdhci-esdhc.h (Reported-by: Bough Chen <haibo.chen@nxp.com>) - placed both control register mask definitions next to each other - fixed timeout write register name - Link to v2: https://lore.kernel.org/r/20241030-imx-emmc-reset-v2-0-b3a823393974@solid-run.com Changes in v2: - replaced udelay with usleep_range (Reported-by: Adrian Hunter <adrian.hunter@intel.com>) - added comments for delay values (Reported-by: Peng Fan <peng.fan@nxp.com>) - delay values based on JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, on page 159 (Thanks to Bough Chen <haibo.chen@nxp.com>) - added a second patch demonstrating a cosmetic issue revealed by first patch - it bothered me during development but is not important - Link to v1: https://lore.kernel.org/r/20241027-imx-emmc-reset-v1-1-d5d0c672864a@solid-run.com --- Josua Mayer (2): mmc: host: sdhci-esdhc-imx: implement emmc hardware reset mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask drivers/mmc/host/sdhci-esdhc-imx.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) --- base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc change-id: 20241027-imx-emmc-reset-7127d311174c Best regards,