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[209.132.180.67]) by mx.google.com with ESMTP id l81si28992469pfi.32.2016.11.07.17.26.03; Mon, 07 Nov 2016 17:26:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752537AbcKHBZo (ORCPT + 3 others); Mon, 7 Nov 2016 20:25:44 -0500 Received: from mail-pf0-f170.google.com ([209.85.192.170]:35185 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752535AbcKHBZn (ORCPT ); Mon, 7 Nov 2016 20:25:43 -0500 Received: by mail-pf0-f170.google.com with SMTP id i88so98058345pfk.2 for ; Mon, 07 Nov 2016 17:25:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ce2ouCt8ZNihef4jqkDW9fHRlhAm+ZgaS+YWTr4zOH4=; b=NW9KR609BHicsKyWt5DAKm+IFZwArlpeuYLfi+IPp3NvC76PMiLsTv/FRYbTRYN5GZ 2z6hPmmW9MhqaE/5es90IM6VbRFZS3pQxddbCHbDPOXDp+OyR69r9HtHEaH0c4IEzP/i NFH1WQwuYg0u3hwapYJm2n/ejvLEDfL76XB2c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ce2ouCt8ZNihef4jqkDW9fHRlhAm+ZgaS+YWTr4zOH4=; b=InxX+HDwxxTh96QX34e3HWMOaEdWG841cdlHNd5YznXP4gWoloBkD+gLnSSY5fLL+2 4InqFid7NNwep3Zy7yteRb2n6vpNO5a0ZHZakUrtVhHA1eod3NH6n11h0ir8cbGDLCoG x6okKlS518oO85Eu1P/SwxXdfasXHaB0/ibpp/Xy/kDr1aY0EPfimKXFd6Mv5PGUjr62 gGd7hwbljSpr7hFnfcK1PaWflMA9NXvMTbUsgBfzlXRXcZnhfYjschLkLN/hgEtoL/3I ygB0jhjYLwznvE4AcE/AJ6hKpqwP3XDNEiGf9jPcSj6/wWZqXoqaF4gG3CDXKSiNgm5r n14Q== X-Gm-Message-State: ABUngvcI+acZxAmleu/xyKmZQEqJwEtJiJQyCrMUZTFZAoBQZozEm92NddLkW3Bxfwk2oQ5j X-Received: by 10.99.125.77 with SMTP id m13mr2902768pgn.58.1478568343192; Mon, 07 Nov 2016 17:25:43 -0800 (PST) Received: from localhost.localdomain ([188.42.255.211]) by smtp.gmail.com with ESMTPSA id a22sm43360056pfg.7.2016.11.07.17.25.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Nov 2016 17:25:42 -0800 (PST) From: Jun Nie To: shawn.guo@linaro.org, xie.baoyou@zte.com.cn Cc: ulf.hansson@linaro.org, jh80.chung@samsung.com, jason.liu@linaro.org, linux-mmc@vger.kernel.org, Jun Nie Subject: [PATCH v5 3/5] Documentation: synopsys-dw-mshc: add binding for fifo quirks Date: Tue, 8 Nov 2016 09:24:56 +0800 Message-Id: <1478568298-18380-4-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478568298-18380-1-git-send-email-jun.nie@linaro.org> References: <1478568298-18380-1-git-send-email-jun.nie@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add fifo-addr property and fifo-watermark-quirk property to synopsys-dw-mshc bindings. It is intended to provide more dt interface to support SoCs specific configuration. Signed-off-by: Jun Nie --- Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index 4e00e85..8bf2e41 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt @@ -76,6 +76,17 @@ Optional properties: * broken-cd: as documented in mmc core bindings. +* data-addr: Override fifo address with value provided by DT. The default FIFO reg + offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by + driver. If the controller does not follow this rule, please use this property + to set fifo address in device tree. + +* fifo-watermark-aligned: Data done irq is expected if data length is less than + watermark in PIO mode. But fifo watermark is requested to be aligned with data + length in some SoC so that TX/RX irq can be generated with data done irq. Add this + watermark quirk to mark this requirement and force fifo watermark setting + accordingly. + * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. @@ -103,6 +114,8 @@ board specific portions as listed below. interrupts = <0 75 0>; #address-cells = <1>; #size-cells = <0>; + data-addr = <0x200>; + fifo-watermark-aligned; }; [board specific internal DMA resources]