From patchwork Wed Jan 25 15:12:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 92461 Delivered-To: patches@linaro.org Received: by 10.140.20.99 with SMTP id 90csp2253712qgi; Wed, 25 Jan 2017 07:12:38 -0800 (PST) X-Received: by 10.25.56.25 with SMTP id f25mr13948069lfa.83.1485357158857; Wed, 25 Jan 2017 07:12:38 -0800 (PST) Return-Path: Received: from mail-lf0-x233.google.com (mail-lf0-x233.google.com. [2a00:1450:4010:c07::233]) by mx.google.com with ESMTPS id r126si14890798lff.7.2017.01.25.07.12.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jan 2017 07:12:38 -0800 (PST) Received-SPF: pass (google.com: domain of ulf.hansson@linaro.org designates 2a00:1450:4010:c07::233 as permitted sender) client-ip=2a00:1450:4010:c07::233; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: domain of ulf.hansson@linaro.org designates 2a00:1450:4010:c07::233 as permitted sender) smtp.mailfrom=ulf.hansson@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by mail-lf0-x233.google.com with SMTP id n124so130207067lfd.2 for ; Wed, 25 Jan 2017 07:12:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P3QgDdPRP3oAP4j3q1lM7jIO4BaD0eet05E6wGGWkwQ=; b=DnQvMb07Lf2rvFuRY14LsgEXImdKiahW95283hkY9cqwMrqX6VULugc1uWTMDZsbaf bCAtB44qr2PgLvz0K23Io1D2voE1ijLpZH8diML2ll3MOu5bqd4tktweFoWBqriReoSj dEeEqptxXWGBMMg1gf5AkS2fPp3LEkO48DD00= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P3QgDdPRP3oAP4j3q1lM7jIO4BaD0eet05E6wGGWkwQ=; b=cbaMZkzeS9YgsPepD82rFEqAwjTTnC1m+xp7k6Ah5dvpOIWggfGG2EMAE1M8Nryv9W gLC/uviG2JPzIGfMjzv30y/WP8pwN4kLDMMMCvmHlk5PxdEMKbS7qtLTFwCLF/Yb7w2a cmfvd/ZBz/4HXc2G3zPK3DYlE6GZwaaxTTjpFIImqt/z7E2fVmdv+qA4cos8Fua4eoHR JuoEggWu/aQHQ5C3EoSBg3ZrjTTyCBRaYidR5vEg7gB9Qrv++XU1rhZfB5BhtA+/bj0I 71/8DoAnc5yQch3/bldAgyG56zQIYpqlR+EsexX3iiQa9VjxIhwv40q/nmZitao3iQNB I1ew== X-Gm-Message-State: AIkVDXIFrESzg9paCLSvk86ahvckvgBN8SMoKYi9q07MF1x1TOL3SD0ppBAgfJxess2gSBu7rGU= X-Received: by 10.46.87.73 with SMTP id r9mr16247765ljd.22.1485357158240; Wed, 25 Jan 2017 07:12:38 -0800 (PST) Return-Path: Received: from uffe-Latitude-E6430s.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id u126sm8397687lja.25.2017.01.25.07.12.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Jan 2017 07:12:37 -0800 (PST) From: Ulf Hansson To: linux-mmc@vger.kernel.org, Ulf Hansson Cc: Jaehoon Chung , Adrian Hunter , Shawn Lin , Stefan Wahren , Fabio Estevam , Jan Glauber Subject: [PATCH 4/6] mmc: core: Invent MMC_CAP_3_3V_DDR Date: Wed, 25 Jan 2017 16:12:21 +0100 Message-Id: <1485357143-23280-5-git-send-email-ulf.hansson@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1485357143-23280-1-git-send-email-ulf.hansson@linaro.org> References: <1485357143-23280-1-git-send-email-ulf.hansson@linaro.org> According the JEDEC specification an eMMC card supporting 1.8V vccq in DDR mode should also be capable of 3.3V. However, it's been reported that some mmc hosts supports 3.3V, but not 1.8V. Currently the mmc core implements an error handling when the host fails to set 1.8V for vccq, by falling back to 3.3V. Unfortunate, this seems to be insufficient for some mmc hosts. To enable these to use eMMC DDR mode let's invent a new mmc cap, MMC_CAP_3_3V_DDR, which tells whether they support the eMMC 3.3V DDR mode. In case MMC_CAP_3_3V_DDR is set, but not MMC_CAP_1_8V_DDR, let's change to remain on the 3.3V, as it's the default voltage level for vccq, set by the earlier power up sequence. As this change introduces MMC_CAP_3_3V_DDR, let's take the opportunity to do some re-formatting of the related defines in the header file. Signed-off-by: Ulf Hansson --- drivers/mmc/core/mmc.c | 11 +++++++---- include/linux/mmc/host.h | 21 ++++++++++----------- 2 files changed, 17 insertions(+), 15 deletions(-) -- 1.9.1 diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 5844f29..f1a451e 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -213,7 +213,7 @@ static void mmc_select_card_type(struct mmc_card *card) avail_type |= EXT_CSD_CARD_TYPE_HS_52; } - if (caps & MMC_CAP_1_8V_DDR && + if (caps & (MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR) && card_type & EXT_CSD_CARD_TYPE_DDR_1_8V) { hs_max_dtr = MMC_HIGH_DDR_MAX_DTR; avail_type |= EXT_CSD_CARD_TYPE_DDR_1_8V; @@ -1120,11 +1120,14 @@ static int mmc_select_hs_ddr(struct mmc_card *card) * * WARNING: eMMC rules are NOT the same as SD DDR */ - err = -EINVAL; - if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_1_2V) + if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_1_2V) { err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120); + if (!err) + return 0; + } - if (err && (card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_1_8V)) + if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_1_8V && + host->caps & MMC_CAP_1_8V_DDR) err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180); /* make sure vccq is 3.3v after switching disaster */ diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 97699d5..83f1c4a 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -259,17 +259,16 @@ struct mmc_host { #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ #define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ -#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ - /* DDR mode at 1.8V */ -#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ - /* DDR mode at 1.2V */ -#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ -#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ -#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ -#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ -#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ -#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ -#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ +#define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */ +#define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */ +#define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */ +#define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */ +#define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */ +#define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */ +#define MMC_CAP_UHS_SDR25 (1 << 17) /* Host supports UHS SDR25 mode */ +#define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */ +#define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */ +#define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */ #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */