From patchwork Tue Mar 9 01:57:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Zhou X-Patchwork-Id: 396383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4D97C433E0 for ; Tue, 9 Mar 2021 02:06:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6540565279 for ; Tue, 9 Mar 2021 02:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229694AbhCICGV (ORCPT ); Mon, 8 Mar 2021 21:06:21 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:34275 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229589AbhCICFz (ORCPT ); Mon, 8 Mar 2021 21:05:55 -0500 X-UUID: 342e29057a7b41cf9ea0c6426665079a-20210309 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=doRoKT02YmY9yqkI9WdPTo7R96qFnA9sunseZ8/VHqs=; b=pHmY/QvbKDhP+TJPzicfKjNWc6HzwpLw2EpCBkksBkkXVq2mIo1cKNwIYwhaYWp7cSmfybefoRKOsXeyvSgFAsnhic8zphaEXUUXtvFJwZhMbVfbmJdb0ur/W/i1JU0ANym/tB8XBiBH0VxvCVeorK3t1lRP5EVYzb0cLO3ZSSs=; X-UUID: 342e29057a7b41cf9ea0c6426665079a-20210309 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 833173208; Tue, 09 Mar 2021 10:05:51 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS32N1.mediatek.inc (172.27.4.71) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Mar 2021 10:05:47 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Mar 2021 10:05:46 +0800 From: Peng Zhou To: Eric Biggers , Ulf Hansson , Chaotian Jing , CC: , Adrian Hunter , Satya Tangirala , Wulin Li , Peng Zhou Subject: [PATCH v2 2/4] mmc: Mediatek: enable crypto hardware engine Date: Tue, 9 Mar 2021 09:57:51 +0800 Message-ID: <20210309015750.6283-1-peng.zhou@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: 5ED153600B6D794E3DDF85777173329FED72E2B9C6542A1C7C67AE0CBB0AA6132000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use SMC call enable hardware crypto engine due to it only be changed in ATF(EL3). Signed-off-by: Peng Zhou --- drivers/mmc/host/mtk-sd.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.18.0 diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 1c90360d6cf2..225ef5519161 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -4,6 +4,7 @@ * Author: Chaotian.Jing */ +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -319,6 +321,12 @@ #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ #define PAD_DELAY_MAX 32 /* PAD delay cells */ + +/*--------------------------------------------------------------------------*/ +/* SiP commands which used for crypto */ +/*--------------------------------------------------------------------------*/ +#define MTK_SIP_MMC_CONTROL MTK_SIP_SMC_CMD(0x273) + /*--------------------------------------------------------------------------*/ /* Descriptor Structure */ /*--------------------------------------------------------------------------*/ @@ -2467,6 +2475,7 @@ static int msdc_of_clock_parse(struct platform_device *pdev, static int msdc_drv_probe(struct platform_device *pdev) { + struct arm_smccc_res smccc_res; struct mmc_host *mmc; struct msdc_host *host; struct resource *res; @@ -2616,6 +2625,15 @@ static int msdc_drv_probe(struct platform_device *pdev) mmc->max_seg_size = 64 * 1024; } + /* + * 1: MSDC_AES_CTL_INIT + * 4: cap_id, no-meaning now + * 1: cfg_id, we choose the second cfg group + */ + if (mmc->caps2 & MMC_CAP2_CRYPTO) + arm_smccc_smc(MTK_SIP_MMC_CONTROL, + 1, 4, 1, 0, 0, 0, 0, &smccc_res); + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc), @@ -2770,9 +2788,18 @@ static int __maybe_unused msdc_runtime_resume(struct device *dev) { struct mmc_host *mmc = dev_get_drvdata(dev); struct msdc_host *host = mmc_priv(mmc); + struct arm_smccc_res smccc_res; msdc_ungate_clock(host); msdc_restore_reg(host); + /* + * 1: MSDC_AES_CTL_INIT + * 4: cap_id, no-meaning now + * 1: cfg_id, we choose the second cfg group + */ + if (mmc->caps2 & MMC_CAP2_CRYPTO) + arm_smccc_smc(MTK_SIP_MMC_CONTROL, + 1, 4, 1, 0, 0, 0, 0, &smccc_res); return 0; }