From patchwork Wed Aug 14 07:29:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Avri Altman X-Patchwork-Id: 819312 Received: from esa1.hgst.iphmx.com (esa1.hgst.iphmx.com [68.232.141.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03721139D00 for ; Wed, 14 Aug 2024 07:31:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.141.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723620693; cv=none; b=HR0XoBGLwQtQlKLe3Vt6lYtAjrVtzYMVEIfig9FyHpoenVCZpa865//njknkjA57G3JFXMVRhsrw7hA56aeW2JGlVOSQGZw7kCJ47zVzFZxMoRKvXYlNOj4B7jpP/Py5rqRbcr5ZN497a8OuAfy6KaF6AcAaIQcQVp7acP5GlX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723620693; c=relaxed/simple; bh=NgjZnbxs4vnM4hrdhiIE/fP5/6bkNcoF+FByTT1q2xg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DisrXhpx8OuoxefE/XpKPghtMNYG8k+0jymv8x4/KaJ+51syMvnHKISUBsEpBpXyXBQoHrPRfBzjxEhPAk+BYspBF8RUod075b/ZC2vdOoayiQ5vmTcodjlX8DGDt8hDGmFahNkeWb610UOHA1Zj3XOTbm7TFnUwMMqThDdW/lA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=wdc.com; spf=pass smtp.mailfrom=wdc.com; dkim=pass (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b=JghS4KRD; arc=none smtp.client-ip=68.232.141.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=wdc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=wdc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="JghS4KRD" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1723620691; x=1755156691; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NgjZnbxs4vnM4hrdhiIE/fP5/6bkNcoF+FByTT1q2xg=; b=JghS4KRD9Z4dWgOw0BYZ4W9e6luPdZ+xucbm64o+Kgrh6Mk2VR3sFqlG fg09jAPDwRDd1DtzmDyg0JBkQkrHmHoGnRLH7m5Mh7+2ik5a8isVv5KCJ WIbKI3Uji+WGV8lOAmtQEETXEu1XpI59kkjDn2crXfF8kMgsgvtJXGCbK GQIQ3e4DAqBvZIgJnIjxo+q+3B/B+YHaUZPG4VJYd/WmXTTWluxZlDgDk O/HP0ummlloliqlYTa+7iFAN8pG5SiizaKr19B8ojxvxqhBSay3iAgXNg nwJ2/5eQPhwJgwxlquhGZrEFOWTK1Y5iY+sUwAsay9zuV/l+p+rboSXsZ g==; X-CSE-ConnectionGUID: +HyL25Z/QFilMAv7hIdpZw== X-CSE-MsgGUID: vN/XGM0OS7Ky7TdZIQohlQ== X-IronPort-AV: E=Sophos;i="6.09,288,1716220800"; d="scan'208";a="24957179" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 14 Aug 2024 15:31:30 +0800 IronPort-SDR: 66bc4f4f_mjr68ZPEhZopJCoOhy5qZSRMu5A2fpKoP7WsRugzfCX/DP5 FmmpeptJzSjltJ5Diw51GT8TZc2PUAuktdb+llA== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 13 Aug 2024 23:31:43 -0700 WDCIronportException: Internal Received: from avri-office.ad.shared (HELO avri-office.sdcorp.global.sandisk.com) ([10.45.31.142]) by uls-op-cesaip02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Aug 2024 00:31:29 -0700 From: Avri Altman To: Ulf Hansson , linux-mmc@vger.kernel.org Cc: Ricky WU , Avri Altman Subject: [PATCH v3 03/10] mmc: sd: Add Extension memory addressing Date: Wed, 14 Aug 2024 10:29:27 +0300 Message-Id: <20240814072934.2559911-4-avri.altman@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240814072934.2559911-1-avri.altman@wdc.com> References: <20240814072934.2559911-1-avri.altman@wdc.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SDUC memory addressing spans beyond 2TB and up to 128TB. Therefore, 38 bits are required to access the entire memory space of all sectors. Those extra 6 bits are to be carried by CMD22 prior of sending read/write/erase commands: CMD17, CMD18, CMD24, CMD25, CMD32, and CMD33. CMD22 will carry the higher order 6 bits, and must precedes any of the above commands even if it targets sector < 2TB. No error related to address or length is indicated in CMD22 but rather in the read/write command itself. Tested-by: Ricky WU Signed-off-by: Avri Altman --- drivers/mmc/core/sd_ops.c | 15 +++++++++++++++ drivers/mmc/core/sd_ops.h | 1 + include/linux/mmc/sd.h | 3 +++ 3 files changed, 19 insertions(+) diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c index 7f6963dac873..8b69129d7b61 100644 --- a/drivers/mmc/core/sd_ops.c +++ b/drivers/mmc/core/sd_ops.c @@ -199,6 +199,21 @@ int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) return 0; } +int mmc_send_ext_addr(struct mmc_host *host, sector_t addr) +{ + struct mmc_command cmd = { + .opcode = SD_ADDR_EXT, + .arg = (u32)((addr >> 32) & 0x3F), + .flags = MMC_RSP_R1 | MMC_CMD_AC, + }; + + if (!mmc_card_is_sduc(host)) + return 0; + + return mmc_wait_for_cmd(host, &cmd, 0); +} +EXPORT_SYMBOL_GPL(mmc_send_ext_addr); + static int __mmc_send_if_cond(struct mmc_host *host, u32 ocr, u8 pcie_bits, u32 *resp) { diff --git a/drivers/mmc/core/sd_ops.h b/drivers/mmc/core/sd_ops.h index 7667fc223b74..462efd43acfa 100644 --- a/drivers/mmc/core/sd_ops.h +++ b/drivers/mmc/core/sd_ops.h @@ -21,6 +21,7 @@ int mmc_send_relative_addr(struct mmc_host *host, unsigned int *rca); int mmc_app_send_scr(struct mmc_card *card); int mmc_app_sd_status(struct mmc_card *card, void *ssr); int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card); +int mmc_send_ext_addr(struct mmc_host *host, sector_t addr); #endif diff --git a/include/linux/mmc/sd.h b/include/linux/mmc/sd.h index 865cc0ca8543..af5fc70e09a2 100644 --- a/include/linux/mmc/sd.h +++ b/include/linux/mmc/sd.h @@ -15,6 +15,9 @@ #define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ #define SD_SWITCH_VOLTAGE 11 /* ac R1 */ +/* Class 2 */ +#define SD_ADDR_EXT 22 /* ac [5:0] R1 */ + /* class 10 */ #define SD_SWITCH 6 /* adtc [31:0] See below R1 */