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Currently the driver accesses those bits by 32-bit write using SDHCI_TIMEOUT_CONTROL (0x2E) defined in drivers/mmc/host/sdhci.h. This is offset by two bytes relative to uSDHCx_SYS_CTRL (0x2C). The driver also defines ESDHC_SYS_CTRL_DTOCV_MASK as first 4 bits, which is correct relative to SDHCI_TIMEOUT_CONTROL but not relative to uSDHCx_SYS_CTRL. The definition carrying control register in its name is therefore inconsistent. Update the bitmask definition for bits 16-19 to be correct relative to control register base. Update the esdhc_set_timeout function to set timeout value at control register base, not timeout offset. This solves a purely cosmetic problem. Signed-off-by: Josua Mayer Reviewed-by: Haibo Chen --- drivers/mmc/host/sdhci-esdhc-imx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index f106e291c276d0c8063e9ac59a126acf5e9e239e..cda3cc4cc22cfa214369f40f097ca50937898604 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -30,7 +30,7 @@ #include "sdhci-esdhc.h" #include "cqhci.h" -#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f +#define ESDHC_SYS_CTRL_DTOCV_MASK GENMASK(19, 16) #define ESDHC_SYS_CTRL_IPP_RST_N BIT(23) #define ESDHC_CTRL_D3CD 0x08 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) @@ -1386,8 +1386,8 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) /* use maximum timeout counter */ esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, - esdhc_is_usdhc(imx_data) ? 0xF : 0xE, - SDHCI_TIMEOUT_CONTROL); + esdhc_is_usdhc(imx_data) ? 0xF0000 : 0xE0000, + ESDHC_SYSTEM_CONTROL); } static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)