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Fri, 01 Nov 2024 03:15:40 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4A13Fe2A010584; Fri, 1 Nov 2024 03:15:40 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-spuppala-hyd.qualcomm.com [10.213.108.54]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 4A13Fe8L010580; Fri, 01 Nov 2024 03:15:40 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 4137148) id 7E08A5006D4; Fri, 1 Nov 2024 08:45:39 +0530 (+0530) From: Seshu Madhavi Puppala To: Adrian Hunter , Asutosh Das , Ulf Hansson Cc: Ritesh Harjani , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_gaurkash@quicinc.com, quic_neersoni@quicinc.com, quic_spuppala@quicinc.com Subject: [PATCH RFC 1/6] mmc: host: support wrapped keys in mmc Date: Fri, 1 Nov 2024 08:45:34 +0530 Message-Id: <20241101031539.13285-2-quic_spuppala@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241101031539.13285-1-quic_spuppala@quicinc.com> References: <20241101031539.13285-1-quic_spuppala@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: lzztYrSkVKLGOFatPZTwKVLBxwkYaroH X-Proofpoint-GUID: lzztYrSkVKLGOFatPZTwKVLBxwkYaroH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1011 mlxlogscore=999 priorityscore=1501 spamscore=0 malwarescore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411010022 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Since wrapped keys are not part of the MMC specifications, it needs to be treated as a supported quirk of the MMC controller. This way, based on the quirk set during a host probe, MMC crypto can choose to register either standard or wrapped keys with block crypto profile. Signed-off-by: Seshu Madhavi Puppala --- drivers/mmc/host/cqhci-crypto.c | 23 +++++++++++++++-------- drivers/mmc/host/cqhci.h | 6 ++++++ 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/host/cqhci-crypto.c b/drivers/mmc/host/cqhci-crypto.c index 91da6de1d650..c4e7ae95bc7d 100644 --- a/drivers/mmc/host/cqhci-crypto.c +++ b/drivers/mmc/host/cqhci-crypto.c @@ -91,13 +91,15 @@ static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile, cfg.crypto_cap_idx = cap_idx; cfg.config_enable = CQHCI_CRYPTO_CONFIGURATION_ENABLE; - if (ccap_array[cap_idx].algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS) { - /* In XTS mode, the blk_crypto_key's size is already doubled */ - memcpy(cfg.crypto_key, key->raw, key->size/2); - memcpy(cfg.crypto_key + CQHCI_CRYPTO_KEY_MAX_SIZE/2, - key->raw + key->size/2, key->size/2); - } else { - memcpy(cfg.crypto_key, key->raw, key->size); + if (key->crypto_cfg.key_type != BLK_CRYPTO_KEY_TYPE_HW_WRAPPED) { + if (ccap_array[cap_idx].algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS) { + /* In XTS mode, the blk_crypto_key's size is already doubled */ + memcpy(cfg.crypto_key, key->raw, key->size/2); + memcpy(cfg.crypto_key + CQHCI_CRYPTO_KEY_MAX_SIZE/2, + key->raw + key->size/2, key->size/2); + } else { + memcpy(cfg.crypto_key, key->raw, key->size); + } } err = cqhci_crypto_program_key(cq_host, key, &cfg, slot); @@ -211,7 +213,12 @@ int cqhci_crypto_init(struct cqhci_host *cq_host) /* Unfortunately, CQHCI crypto only supports 32 DUN bits. */ profile->max_dun_bytes_supported = 4; - profile->key_types_supported = BLK_CRYPTO_KEY_TYPE_STANDARD; + if (cq_host->quirks & CQHCI_QUIRK_USES_WRAPPED_CRYPTO_KEYS) + profile->key_types_supported = + BLK_CRYPTO_KEY_TYPE_HW_WRAPPED; + else + profile->key_types_supported = + BLK_CRYPTO_KEY_TYPE_STANDARD; /* * Cache all the crypto capabilities and advertise the supported crypto diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index 06099fd32f23..f6bc66bc6418 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -241,6 +241,12 @@ struct cqhci_host { u32 quirks; #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1 + /* + * This quirk indicates that EMMC will be using HW wrapped keys + * when using inline encryption. + */ +#define CQHCI_QUIRK_USES_WRAPPED_CRYPTO_KEYS 0x2 + bool enabled; bool halted; bool init_done;