From patchwork Sun Mar 9 05:53:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Zi X-Patchwork-Id: 872368 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C5D8126C02; Sun, 9 Mar 2025 05:55:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741499733; cv=none; b=diQ9F0DaYUx9+RCcI8n+mRuIDLjvkfwbsNA+Bp80Xwcr5jc+Pr3FIUM8o5sf0ClQfT8mht2Cq7aEAfm627GcLxYaBTSV8vq8ydRLtGIC3ceC5kLl1lNw8ohpPpRncVPpSLqb8Xi4JhEm5m2+mJe88oH+wAFDflw1Xp0DCFVa0EY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741499733; c=relaxed/simple; bh=txtgvCyVbTCcdPGfG+8cSd9zAfYuSNsflYj4tJgx2Ao=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HdpI7sDrIB/so3dF8wLs4T/9DLRu64oT0rKdv30UWEwonG8XNjPKPtx0eBddfK3HncBAODT32fc71pCy3f1cQEETlkr0Kw7SzN9sUuGPPME202eqLuwCCPeNUEwR/UDZhjv6fkn2QoIHsMkLov9pFsy6er4SZFAK4OT7CVSB2SM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ZwI+2n1X; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ZwI+2n1X" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 03CAA25984; Sun, 9 Mar 2025 06:55:30 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id kG-bdOTiKFOl; Sun, 9 Mar 2025 06:55:25 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1741499725; bh=txtgvCyVbTCcdPGfG+8cSd9zAfYuSNsflYj4tJgx2Ao=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ZwI+2n1XdJ/Bn1htpW4EPh8cqXkz7wWfZDuiv8DwlRxReiqUxRkEK0UYyF1lqkaZH LD8DLhDSqdSxvG/+YRpjRVuEtv2kJJQJ47ZqaJmQ+W0vBeMKoYo7xg4U/nW6lpS3Ac kSXUwstqio6QKzG5uhYCczjJ9gkHb/8QpOybXi3Sa2IdF+HRU4PE9fqF0S0VjdhIFQ aoFd3shXOffqVzIuWNReU83QuN/ZkfxGJJafrzeHqolwpukR4+pIkF1wzhHK1qtXRs 4mLGa7SIYg2IyqY58gXc7YcUgTJ912pgcP669KKt2O572+/ZqFIyJ3FM3usH8ydsab ex+Bf+lMHWn7Q== From: Yao Zi To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Michael Turquette , Stephen Boyd , Shresth Prasad , Cristian Ciocaltea , Detlev Casanova , Jonas Karlman , Chukun Pan Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Yao Zi Subject: [PATCH v3 5/6] arm64: dts: rockchip: Add SDMMC/SDIO controllers for RK3528 Date: Sun, 9 Mar 2025 05:53:47 +0000 Message-ID: <20250309055348.9299-6-ziyao@disroot.org> In-Reply-To: <20250309055348.9299-1-ziyao@disroot.org> References: <20250309055348.9299-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 RK3528 features two SDIO controllers and one SD/MMC controller, describe them in devicetree. Since their sample and drive clocks are located in the VO and VPU GRFs, corresponding syscons are added to make these clocks available. Signed-off-by: Yao Zi --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 69 ++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index c2eaa0c6ea90..04ca2e2b3e9b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -321,6 +321,16 @@ qos_vpu: qos@ff280400 { reg = <0x0 0xff280400 0x0 0x20>; }; + vpu_grf: syscon@ff340000 { + compatible = "rockchip,rk3528-vpu-grf", "syscon"; + reg = <0x0 0xff340000 0x0 0x8000>; + }; + + vo_grf: syscon@ff360000 { + compatible = "rockchip,rk3528-vo-grf", "syscon"; + reg = <0x0 0xff360000 0x0 0x10000>; + }; + cru: clock-controller@ff4a0000 { compatible = "rockchip,rk3528-cru"; reg = <0x0 0xff4a0000 0x0 0x30000>; @@ -468,6 +478,65 @@ saradc: adc@ffae0000 { status = "disabled"; }; + sdio0: mmc@ffc10000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc10000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO0>, + <&cru CCLK_SRC_SDIO0>, + <&cru SCLK_SDIO0_DRV>, + <&cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; + resets = <&cru SRST_H_SDIO0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio1: mmc@ffc20000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc20000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO1>, + <&cru CCLK_SRC_SDIO1>, + <&cru SCLK_SDIO1_DRV>, + <&cru SCLK_SDIO1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; + resets = <&cru SRST_H_SDIO1>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc: mmc@ffc30000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc30000 0x0 0x4000>; + clocks = <&cru HCLK_SDMMC0>, + <&cru CCLK_SRC_SDMMC0>, + <&cru SCLK_SDMMC_DRV>, + <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, + <&sdmmc_det>; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + rockchip,default-sample-phase = <90>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3528-pinctrl"; rockchip,grf = <&ioc_grf>;