From patchwork Thu Jun 12 18:56:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 895829 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5EA02D1F72; Thu, 12 Jun 2025 19:01:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749754899; cv=pass; b=ueZdeTWeaMl43khmj/oVz2jBGXHikdyF7/1nUvCOpdNIRlXhvX0LPX7Ve0iL/QW9QlBMx42FOJ5RkNtAiZZJnRZgbhUTyB8/Phi3svmyzGvET1zsaAkSOmJpCFhi6fc2deMhjdf8nVCdOAl/j0gg3rcD0XSSzA93iE8W+F2d1h0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749754899; c=relaxed/simple; bh=3l2/382oXuQckHXMcFNIdMBsrBifyDFF2nWhSPoo8ZQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TnQvSR3mzW+doEbwhwOkqC+NKtNLmDwZ9kUmvI2lIufvP5Xko6Yo/ySyXg9VHHBbwD18Hcq6PMQBVshQXYuyJw6EYePml8w3dcbVYW5dq2kjTIK1kxk/+2hss1IU3HUYEtRriRXjhv5k5+D+O2L+CQgKLTAPEur6GJSpyf8Hpj0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=fu5lzhx6; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="fu5lzhx6" ARC-Seal: i=1; a=rsa-sha256; t=1749754835; cv=none; d=zohomail.com; s=zohoarc; b=Iw4lh31zL3z3vD4l4xecCrI7P32xZo18/XnWLSbT+0eTjO8AWIJ+cpqks4s0BYoN9xlYeef1j2egzjwr6MmP242NVMt//uQiPxgKLyzoNTH4hU3jXrdsmZirqu/Ue7iru8typnlh6/GgxJJa3X1fE49YengG5j96Ugpj76FUWzw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1749754835; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=A3pFEOOb6EOrxgekJ/E7bblmTlxsE0jgmWgpDuqVGPI=; b=l3U8SXUOPY1cFZ6FfLwBTFMZqMXPT4oGoyfyIaDbxLbWbmdL58lG2nR+SztDNwooTh0adAGz2h9vpOvOODttWauvs36n5sq9mmxO1Y26JMmhGclvz9wlEP/ktsgkYfzqRWGT3VpIQSde8ouA3yx2aRn1kQE9KM+URDXK4Pu3wZ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1749754835; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=A3pFEOOb6EOrxgekJ/E7bblmTlxsE0jgmWgpDuqVGPI=; b=fu5lzhx6cwwOCtOY33CFP1xl/7xxfxNMI12CKuai1Aw50ZX3m4vX9GQ+GHa8gkyy tjP3stEhr5lch37RCITLb9C7G6w3oPtG17AvoZ39Uazn47g4KXiuzCWG2ydoS+PKnm6 0QxRTMRWkR6Oel4nmpTjlFejoX07IM+z0gAl4Qy8= Received: by mx.zohomail.com with SMTPS id 1749754833329406.383279922641; Thu, 12 Jun 2025 12:00:33 -0700 (PDT) From: Nicolas Frattaroli Date: Thu, 12 Jun 2025 20:56:21 +0200 Subject: [PATCH 19/20] clk: sp7021: switch to HWORD_UPDATE macro Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250612-byeword-update-v1-19-f4afb8f6313f@collabora.com> References: <20250612-byeword-update-v1-0-f4afb8f6313f@collabora.com> In-Reply-To: <20250612-byeword-update-v1-0-f4afb8f6313f@collabora.com> To: Yury Norov , Rasmus Villemoes , Jaehoon Chung , Ulf Hansson , Heiko Stuebner , Shreeya Patel , Mauro Carvalho Chehab , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Vinod Koul , Kishon Vijay Abraham I , Nicolas Frattaroli , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Qin Jian , Michael Turquette , Stephen Boyd , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-sound@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, llvm@lists.linux.dev, Nicolas Frattaroli X-Mailer: b4 0.14.2 The sp7021 clock driver has its own shifted high word mask macro, similar to the ones many Rockchip drivers have. Remove it, and replace instances of it with bitfield.h's HWORD_UPDATE macro, which does the same thing except in a common macro that also does compile-time error checking. This was compile-tested with 32-bit ARM with Clang, no runtime tests were performed as I lack the hardware. However, I verified that fix commit 5c667d5a5a3e ("clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()") is not regressed. No warning is produced. Signed-off-by: Nicolas Frattaroli --- drivers/clk/clk-sp7021.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c index 7cb7d501d7a6ebffe002f80dfa937365e04d356a..f408109f866c6ee65398d549e76994e54c1421ea 100644 --- a/drivers/clk/clk-sp7021.c +++ b/drivers/clk/clk-sp7021.c @@ -38,13 +38,6 @@ enum { #define MASK_DIVN GENMASK(7, 0) #define MASK_DIVM GENMASK(14, 8) -/* HIWORD_MASK FIELD_PREP */ -#define HWM_FIELD_PREP(mask, value) \ -({ \ - u64 _m = mask; \ - (_m << 16) | FIELD_PREP(_m, value); \ -}) - struct sp_pll { struct clk_hw hw; void __iomem *reg; @@ -313,15 +306,15 @@ static int plltv_set_rate(struct sp_pll *clk) u32 r0, r1, r2; r0 = BIT(clk->bp_bit + 16); - r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]); - r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]); - r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]); - r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]); + r0 |= HWORD_UPDATE(MASK_SEL_FRA, clk->p[SEL_FRA]); + r0 |= HWORD_UPDATE(MASK_SDM_MOD, clk->p[SDM_MOD]); + r0 |= HWORD_UPDATE(MASK_PH_SEL, clk->p[PH_SEL]); + r0 |= HWORD_UPDATE(MASK_NFRA, clk->p[NFRA]); - r1 = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]); + r1 = HWORD_UPDATE(MASK_DIVR, clk->p[DIVR]); - r2 = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1); - r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1); + r2 = HWORD_UPDATE(MASK_DIVN, clk->p[DIVN] - 1); + r2 |= HWORD_UPDATE(MASK_DIVM, clk->p[DIVM] - 1); spin_lock_irqsave(&clk->lock, flags); writel(r0, clk->reg);