From patchwork Mon Jul 16 11:01:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 10006 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CB03F24027 for ; Mon, 16 Jul 2012 11:02:21 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 79698A184E9 for ; Mon, 16 Jul 2012 11:02:21 +0000 (UTC) Received: by yenq6 with SMTP id q6so5207869yen.11 for ; Mon, 16 Jul 2012 04:02:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=ziCInHJtK2lF6fBiiYEE/N+IEXoyzWtdv93pbYSd5gQ=; b=EJvlkNGXUUo6g+udijy5xZ2kuMXzFvS8Ua1L4apyIg/DmgM/4HR7REX8nyZNv0yyrm QJWxoIHjm85l9UfFrAsYLYnTL+erht0aU+akB1rZwwb8qg8nj0qlalb+CJ5oyJt2cg9j ca6zeU4ER8DaHTufNbAQulT0qm16BM4EhPjAVfXjS9zYdTw9Ujl+WEj6H2on7k6apc+4 mxg/T9sIWG0Y3F2HDqSS5ClZXiwTJlqsHNoUFB4WVaDm/8bfgWtH/cSm/k81RizN6yyE NnEGY/vgDxZpt+mRUjaw1WWsQ95DCBiX8P4E2CS4lOP0ZaAdjZQ9EWMptN2A/6aLKVgJ m7Qg== Received: by 10.42.155.73 with SMTP id t9mr5506363icw.48.1342436540714; Mon, 16 Jul 2012 04:02:20 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.241.2 with SMTP id lc2csp6840ibb; Mon, 16 Jul 2012 04:02:19 -0700 (PDT) Received: by 10.236.185.198 with SMTP id u46mr8987086yhm.33.1342436539531; Mon, 16 Jul 2012 04:02:19 -0700 (PDT) Received: from mail-yx0-f178.google.com (mail-yx0-f178.google.com [209.85.213.178]) by mx.google.com with ESMTPS id m15si1547845ang.74.2012.07.16.04.02.19 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 16 Jul 2012 04:02:19 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.213.178 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) client-ip=209.85.213.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.213.178 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) smtp.mail=sachin.kamat@linaro.org Received: by yenl6 with SMTP id l6so5696333yen.37 for ; Mon, 16 Jul 2012 04:02:19 -0700 (PDT) Received: by 10.66.83.226 with SMTP id t2mr21890095pay.38.1342436538891; Mon, 16 Jul 2012 04:02:18 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id rg10sm11696341pbc.54.2012.07.16.04.02.15 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 16 Jul 2012 04:02:18 -0700 (PDT) From: Sachin Kamat To: linux-mtd@lists.infradead.org Cc: dwmw2@infradead.org, David.Woodhouse@intel.com, ben-linux@fluff.org, sachin.kamat@linaro.org, patches@linaro.org Subject: [PATCH 4/6][Resend] mtd: s3c2410: Do not initialise statics to 0 or NULL Date: Mon, 16 Jul 2012 16:31:44 +0530 Message-Id: <1342436504-15163-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Gm-Message-State: ALoCoQl1byRsJQl3v88FlaV/JNZ//0RSlgk0mp87c6E+3PIR1QYJKM5xfZ34rZ2/ErBPuINzd5s2 Fixes the following checkpatch errors: ERROR: do not initialise statics to 0 or NULL +static int hardware_ecc = 0; ERROR: do not initialise statics to 0 or NULL +static const int clock_stop = 0; Signed-off-by: Sachin Kamat --- Please ignore the previous patch (v1). This patch takes care of some compilation warnings introduced earlier. --- drivers/mtd/nand/s3c2410.c | 66 +++++++++++++++++++------------------------ 1 files changed, 29 insertions(+), 37 deletions(-) diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 5907d1c..05fb4f7 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -49,19 +49,6 @@ #include #include -#ifdef CONFIG_MTD_NAND_S3C2410_HWECC -static int hardware_ecc = 1; -#else -static int hardware_ecc = 0; -#endif - -#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP -static const int clock_stop = 1; -#else -static const int clock_stop = 0; -#endif - - /* new oob placement block for use with hardware ecc generation */ @@ -170,7 +157,11 @@ static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) static inline int allow_clk_suspend(struct s3c2410_nand_info *info) { - return clock_stop; +#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP + return 1; +#else + return 0; +#endif } /** @@ -452,6 +443,7 @@ static int s3c2412_nand_devready(struct mtd_info *mtd) /* ECC handling functions */ +#ifdef CONFIG_MTD_NAND_S3C2410_HWECC static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { @@ -601,6 +593,7 @@ static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u return 0; } +#endif /* over-ride the standard functions for a little more speed. We can * use read/write block to move the data buffers to/from the controller @@ -821,32 +814,31 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, nmtd->mtd.owner = THIS_MODULE; nmtd->set = set; - if (hardware_ecc) { +#ifdef CONFIG_MTD_NAND_S3C2410_HWECC + chip->ecc.calculate = s3c2410_nand_calculate_ecc; + chip->ecc.correct = s3c2410_nand_correct_data; + chip->ecc.mode = NAND_ECC_HW; + chip->ecc.strength = 1; + + switch (info->cpu_type) { + case TYPE_S3C2410: + chip->ecc.hwctl = s3c2410_nand_enable_hwecc; chip->ecc.calculate = s3c2410_nand_calculate_ecc; - chip->ecc.correct = s3c2410_nand_correct_data; - chip->ecc.mode = NAND_ECC_HW; - chip->ecc.strength = 1; - - switch (info->cpu_type) { - case TYPE_S3C2410: - chip->ecc.hwctl = s3c2410_nand_enable_hwecc; - chip->ecc.calculate = s3c2410_nand_calculate_ecc; - break; - - case TYPE_S3C2412: - chip->ecc.hwctl = s3c2412_nand_enable_hwecc; - chip->ecc.calculate = s3c2412_nand_calculate_ecc; - break; - - case TYPE_S3C2440: - chip->ecc.hwctl = s3c2440_nand_enable_hwecc; - chip->ecc.calculate = s3c2440_nand_calculate_ecc; - break; + break; - } - } else { - chip->ecc.mode = NAND_ECC_SOFT; + case TYPE_S3C2412: + chip->ecc.hwctl = s3c2412_nand_enable_hwecc; + chip->ecc.calculate = s3c2412_nand_calculate_ecc; + break; + + case TYPE_S3C2440: + chip->ecc.hwctl = s3c2440_nand_enable_hwecc; + chip->ecc.calculate = s3c2440_nand_calculate_ecc; + break; } +#else + chip->ecc.mode = NAND_ECC_SOFT; +#endif if (set->ecc_layout != NULL) chip->ecc.layout = set->ecc_layout;