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[65.50.211.133]) by mx.google.com with ESMTPS id j1si317753pfb.208.2017.04.19.00.08.13 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Apr 2017 00:08:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mtd-bounces+patch=linaro.org@lists.infradead.org designates 65.50.211.133 as permitted sender) client-ip=65.50.211.133; Authentication-Results: mx.google.com; dkim=pass header.i=@lists.infradead.org; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-mtd-bounces+patch=linaro.org@lists.infradead.org designates 65.50.211.133 as permitted sender) smtp.mailfrom=linux-mtd-bounces+patch=linaro.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=n+bI0sqHdUb+GSEjB6QzprJTjEgxzeCSfzUJ58NfQuY=; b=jfXjphzQly6+oAo+Rwrcj9ZfZQ PwpfaEA6iNGD03YTQ7vB+kSbmMa48EX5jgxdat0AnGI4jXvgjHkXG7D8HetwfCOffgdWMqoCdhP5z +OsStXcTh6rRr74o2RUeNwTeyHUtKPKU1ThhWtqiSifvB/7t7AfsgeJhWgu3QpowjrZq5MexBpIhO RlKW2YzcCTBVR3aZFPuADHApH8zAS3zhAhh37TyfPUp1WFkkoclRfOCuUhzTpJ5xJrXxDs64xPxBN LzG6P+teaI2eNNNFbfAm95MAz3bhFeov9pWlLvM1H+taALsKDG8285MMfcoDMiGTkznKW+MgWkx62 snuqt5tw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1d0jii-0008Ez-Iv; Wed, 19 Apr 2017 07:08:08 +0000 Received: from conuserg-10.nifty.com ([210.131.2.77]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1d0jie-0008DJ-C5 for linux-mtd@lists.infradead.org; Wed, 19 Apr 2017 07:08:06 +0000 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v3J771hX010893; Wed, 19 Apr 2017 16:07:03 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v3J771hX010893 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1492585623; bh=2wEAsJuQKEwxG5bxxUHEotuVaaoxllRi51LNH+315e4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vtPRkqRLSwBePDC7vyKDjtdQvxlV6EcXeiAlM6c20Nt4FTzDZ/yjPKYibPXxx+Y/r xklhL5wlZgtl1YYDk5hxjvHXTQFIklK8ltCVDhXujcX7EgBu5j7K5MB7fPlZ68PcBD 9COzbHKys250dVfHXcaTY8Q/VXkExHKnH6yzlHLIDJWm898KJpyzfTcwhLL+XavDNd SrU20J5Q/me77UHfAe0HwjPRRpMKJ+P/THSsaMx0wWudHqSTyVyiZad8kwTfvT6lwo 6+eLK8Q5SVR1EXyH6JgQ0Qyf7oC/B3SnqfjjXKrqy+RXXkU6vUuMsK6sbMA8k4S1NM dRjKdHFVhzDeg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Subject: [PATCH 1/2] mtd: nand: add generic helpers to check, match, maximize ECC settings Date: Wed, 19 Apr 2017 16:06:57 +0900 Message-Id: <1492585618-13655-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492585618-13655-1-git-send-email-yamada.masahiro@socionext.com> References: <1492585618-13655-1-git-send-email-yamada.masahiro@socionext.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170419_000804_780103_2CE3255B X-CRM114-Status: GOOD ( 18.50 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Boris Brezillon , Richard Weinberger , Dinh Nguyen , Masahiro Yamada , Artem Bityutskiy , Cyrille Pitchen , linux-kernel@vger.kernel.org, Marek Vasut , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Brian Norris , Enrico Jorns , David Woodhouse , Graham Moore MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+patch=linaro.org@lists.infradead.org Each driver has been responsible for: - Check if ECC setting specified (mostly by DT) is valid - Meet the chip's required ECC strength - Maximize the strength when NAND_ECC_MAXIMIZE flag is set The logic can be generalized by factoring out driver-specific parameters. A driver provides: - Array of (step_size, strength) supported on the controller - A hook that calculates ECC bytes from the combination of (step_size, strength). Then, this commit provides 3 helper functions: nand_check_ecc_caps - Check if preset (step_size, strength) is valid nand_try_to_match_ecc_req - Match the chip's requirement nand_try_to_maximize_ecc - Maximize the ECC strength These helpers will save duplicated code among drivers. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/nand_base.c | 178 +++++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/nand.h | 31 ++++++++ 2 files changed, 209 insertions(+) -- 2.7.4 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 0670e13..ee43e5e 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -4539,6 +4539,184 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd) } } +/** + * nand_check_ecc_caps - check if ECC step size and strength is supported + * @mtd: mtd info structure + * @chip: nand chip info structure + * @caps: ECC engine caps info structure + * + * When ECC step size and strength are set, check if the combination is really + * supported by the controller and fit within the chip's OOB. On success, + * ECC bytes per step is set. + */ +int nand_check_ecc_caps(struct mtd_info *mtd, struct nand_chip *chip, + const struct nand_ecc_engine_caps *caps) +{ + const struct nand_ecc_setting *setting; + int preset_step = chip->ecc.size; + int preset_strength = chip->ecc.strength; + int ecc_bytes; + + if (!preset_step || !preset_strength) + return -ENODATA; + + for (setting = caps->ecc_settings; setting->step; setting++) { + if (setting->step != preset_step || + setting->strength != preset_strength) + continue; + + ecc_bytes = caps->calc_ecc_bytes(setting); + if (WARN_ON_ONCE(ecc_bytes < 0)) + continue; + + if (ecc_bytes * mtd->writesize / setting->step > + caps->avail_oobsize) { + pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", + setting->step, setting->strength); + return -ENOSPC; + } + + chip->ecc.bytes = ecc_bytes; + return 0; + } + + pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", + preset_step, preset_strength); + + return -ENOTSUPP; +} + +/** + * nand_try_to_match_ecc_req - meet the chip's requirement with least ECC bytes + * @mtd: mtd info structure + * @chip: nand chip info structure + * @caps: ECC engine caps info structure + * + * If chip's ECC requirement is available, try to meet it with the least number + * number of ECC bytes (i.e. with the largest number of OOB-free bytes). + * On success, the chosen ECC settings are set. + */ +int nand_try_to_match_ecc_req(struct mtd_info *mtd, struct nand_chip *chip, + const struct nand_ecc_engine_caps *caps) +{ + const struct nand_ecc_setting *setting, *best_setting = NULL; + int req_step = chip->ecc_step_ds; + int req_strength = chip->ecc_strength_ds; + int req_corr, steps, ecc_bytes, ecc_bytes_total; + int best_ecc_bytes, best_ecc_bytes_total = INT_MAX; + + /* No information provided by the NAND chip */ + if (!req_step || !req_strength) + return -ENOTSUPP; + + /* number of correctable bits the chip requires in a page */ + req_corr = mtd->writesize / req_step * req_strength; + + for (setting = caps->ecc_settings; setting->step; setting++) { + /* If chip->ecc.size is already set, respect it. */ + if (chip->ecc.size && setting->step != chip->ecc.size) + continue; + + /* If chip->ecc.strength is already set, respect it. */ + if (chip->ecc.strength && + setting->strength != chip->ecc.strength) + continue; + + /* + * If the controller's step size is smaller than the chip's + * requirement, comparison of the strength is not simple. + */ + if (setting->step < req_step) + continue; + + steps = mtd->writesize / setting->step; + + ecc_bytes = caps->calc_ecc_bytes(setting); + if (WARN_ON_ONCE(ecc_bytes < 0)) + continue; + ecc_bytes_total = ecc_bytes * steps; + + if (ecc_bytes_total > caps->avail_oobsize || + setting->strength * steps < req_corr) + continue; + + /* + * We assume the best is to meet the chip's requrement + * with the least number of ECC bytes. + */ + if (ecc_bytes_total < best_ecc_bytes_total) { + best_ecc_bytes_total = ecc_bytes_total; + best_setting = setting; + best_ecc_bytes = ecc_bytes; + } + } + + if (!best_setting) + return -ENOTSUPP; + + chip->ecc.size = best_setting->step; + chip->ecc.strength = best_setting->strength; + chip->ecc.bytes = best_ecc_bytes; + + return 0; +} +EXPORT_SYMBOL_GPL(nand_try_to_match_ecc_req); + +/** + * nand_try_to_maximize_ecc - choose the max ECC strength available + * @mtd: mtd info structure + * @chip: nand chip info structure + * @caps: ECC engine caps info structure + * + * Choose the max ECC strength that is supported on the controller, and can fit + * within the chip's OOB. * On success, the chosen ECC settings are set. + */ +int nand_try_to_maximize_ecc(struct mtd_info *mtd, struct nand_chip *chip, + const struct nand_ecc_engine_caps *caps) +{ + const struct nand_ecc_setting *setting, *best_setting = NULL; + int steps, ecc_bytes, corr; + int best_corr = 0; + int best_ecc_bytes; + + for (setting = caps->ecc_settings; setting->step; setting++) { + /* If chip->ecc.size is already set, respect it. */ + if (chip->ecc.size && setting->step != chip->ecc.size) + continue; + + steps = mtd->writesize / setting->step; + ecc_bytes = caps->calc_ecc_bytes(setting); + if (WARN_ON_ONCE(ecc_bytes < 0)) + continue; + + if (ecc_bytes * steps > caps->avail_oobsize) + continue; + + corr = setting->strength * steps; + + /* + * If the number of correctable bits is the same, + * bigger ecc_step has more reliability. + */ + if (corr > best_corr || + (corr == best_corr && setting->step > best_setting->step)) { + best_corr = corr; + best_setting = setting; + best_ecc_bytes = ecc_bytes; + } + } + + if (!best_setting) + return -ENOTSUPP; + + chip->ecc.size = best_setting->step; + chip->ecc.strength = best_setting->strength; + chip->ecc.bytes = best_ecc_bytes; + + return 0; +} +EXPORT_SYMBOL_GPL(nand_try_to_maximize_ecc); + /* * Check if the chip configuration meet the datasheet requirements. diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 2ae781e..394128f 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -486,6 +486,28 @@ static inline void nand_hw_control_init(struct nand_hw_control *nfc) } /** + * struct nand_ecc_setting - information of ECC step supported by ECC engine + * @step: data bytes per ECC step + * @bytes: ECC bytes per step + */ +struct nand_ecc_setting { + int step; + int strength; +}; + +/** + * struct nand_ecc_engine_caps - capability of ECC engine + * @ecc_settings: array of (step, strength) supported by this ECC engine + * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step + * @avail_oobsize: OOB size that the ECC engine can use for ECC correction + */ +struct nand_ecc_engine_caps { + const struct nand_ecc_setting *ecc_settings; + int (*calc_ecc_bytes)(const struct nand_ecc_setting *ecc_setting); + int avail_oobsize; +}; + +/** * struct nand_ecc_ctrl - Control structure for ECC * @mode: ECC mode * @algo: ECC algorithm @@ -1208,6 +1230,15 @@ int nand_check_erased_ecc_chunk(void *data, int datalen, void *extraoob, int extraooblen, int threshold); +int nand_check_ecc_caps(struct mtd_info *mtd, struct nand_chip *chip, + const struct nand_ecc_engine_caps *caps); + +int nand_try_to_match_ecc_req(struct mtd_info *mtd, struct nand_chip *chip, + const struct nand_ecc_engine_caps *caps); + +int nand_try_to_maximize_ecc(struct mtd_info *mtd, struct nand_chip *chip, + const struct nand_ecc_engine_caps *caps); + /* Default write_oob implementation */ int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);