| Message ID | 20200713110141.13156-1-kishon@ti.com |
|---|---|
| Headers | show |
| Series | Add PCIe support to TI's J721E SoC | expand |
Hi Lorenzo, On 7/21/2020 9:19 PM, Lorenzo Pieralisi wrote: > On Mon, Jul 13, 2020 at 04:31:30PM +0530, Kishon Vijay Abraham I wrote: >> Certain platforms like TI's J721E using Cadence PCIe IP can perform only >> 32-bit accesses for reading or writing to Cadence registers. Convert all >> read and write accesses to 32-bit in Cadence PCIe driver in preparation >> for adding PCIe support in TI's J721E SoC. >> >> Also add spin lock to disable interrupts while modifying PCI_STATUS >> register while raising legacy interrupt since PCI_STATUS is accessible >> by both remote RC and EP and time between read and write should be >> minimized. >> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> --- >> .../pci/controller/cadence/pcie-cadence-ep.c | 4 + >> drivers/pci/controller/cadence/pcie-cadence.h | 76 ++++++++++++++----- >> 2 files changed, 62 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c >> index 4a829ccff7d0..c6eb2db94680 100644 >> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c >> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c >> @@ -228,6 +228,7 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, >> u8 intx, bool is_asserted) >> { >> struct cdns_pcie *pcie = &ep->pcie; >> + unsigned long flags; >> u32 offset; >> u16 status; >> u8 msg_code; >> @@ -252,11 +253,13 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, >> msg_code = MSG_CODE_DEASSERT_INTA + intx; >> } >> >> + spin_lock_irqsave(&ep->lock, flags); >> status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); >> if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) { >> status ^= PCI_STATUS_INTERRUPT; >> cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); >> } >> + spin_unlock_irqrestore(&ep->lock, flags); >> >> offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | >> CDNS_PCIE_NORMAL_MSG_CODE(msg_code) | >> @@ -464,6 +467,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) >> ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; >> /* Reserve region 0 for IRQs */ >> set_bit(0, &ep->ob_region_map); >> + spin_lock_init(&ep->lock); >> >> return 0; >> >> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h >> index bc49c22e48a9..a45c11158f49 100644 >> --- a/drivers/pci/controller/cadence/pcie-cadence.h >> +++ b/drivers/pci/controller/cadence/pcie-cadence.h >> @@ -304,6 +304,9 @@ struct cdns_pcie_rc { >> * @irq_pci_fn: the latest PCI function that has updated the mapping of >> * the MSI/legacy IRQ dedicated outbound region. >> * @irq_pending: bitmask of asserted legacy IRQs. >> + * @lock: spin lock to disable interrupts while modifying PCIe controller >> + * registers fields (RMW) accessible by both remote RC and EP to >> + * minimize time between read and write >> */ >> struct cdns_pcie_ep { >> struct cdns_pcie pcie; >> @@ -315,54 +318,94 @@ struct cdns_pcie_ep { >> u64 irq_pci_addr; >> u8 irq_pci_fn; >> u8 irq_pending; >> + /* protect writing to PCI_STATUS while raising legacy interrupts */ >> + spinlock_t lock; >> }; >> >> >> /* Register access */ >> -static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) >> +static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) >> { >> - writeb(value, pcie->reg_base + reg); >> + writel(value, pcie->reg_base + reg); >> } >> >> -static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value) >> +static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) >> { >> - writew(value, pcie->reg_base + reg); >> + return readl(pcie->reg_base + reg); >> } >> >> -static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) >> +static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) >> { >> - writel(value, pcie->reg_base + reg); >> + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); >> + unsigned int offset = (unsigned long)addr & 0x3; >> + u32 val = readl(aligned_addr); >> + >> + if (!IS_ALIGNED((uintptr_t)addr, size)) { >> + WARN(1, "Address %p and size %d are not aligned\n", addr, size); > > This is overkill - please consider a less severe logging (eg pr_warn()). > > https://www.kernel.org/doc/html/latest/process/deprecated.html Sure, I'll resend after changing this. > > Same below. I can make these changes before applying but the series > does not apply to v5.8-rc1, please rebase it and I will apply then. Looks like one more patch I have to include in this series [1]. Thanks Kishon [1] -> http://lore.kernel.org/r/20200521080153.5902-1-kishon@ti.com > > Thanks, > Lorenzo > >> + return 0; >> + } >> + >> + if (size > 2) >> + return val; >> + >> + return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); >> } >> >> -static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) >> +static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value) >> { >> - return readl(pcie->reg_base + reg); >> + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); >> + unsigned int offset = (unsigned long)addr & 0x3; >> + u32 mask; >> + u32 val; >> + >> + if (!IS_ALIGNED((uintptr_t)addr, size)) { >> + WARN(1, "Address %p and size %d are not aligned\n", addr, size); >> + return; >> + } >> + >> + if (size > 2) { >> + writel(value, addr); >> + return; >> + } >> + >> + mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); >> + val = readl(aligned_addr) & mask; >> + val |= value << (offset * 8); >> + writel(val, aligned_addr); >> } >> >> /* Root Port register access */ >> static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, >> u32 reg, u8 value) >> { >> - writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); >> + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; >> + >> + cdns_pcie_write_sz(addr, 0x1, value); >> } >> >> static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, >> u32 reg, u16 value) >> { >> - writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); >> + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; >> + >> + cdns_pcie_write_sz(addr, 0x2, value); >> } >> >> /* Endpoint Function register access */ >> static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, >> u32 reg, u8 value) >> { >> - writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); >> + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; >> + >> + cdns_pcie_write_sz(addr, 0x1, value); >> } >> >> static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, >> u32 reg, u16 value) >> { >> - writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); >> + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; >> + >> + cdns_pcie_write_sz(addr, 0x2, value); >> } >> >> static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, >> @@ -371,14 +414,11 @@ static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, >> writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); >> } >> >> -static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg) >> -{ >> - return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); >> -} >> - >> static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) >> { >> - return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); >> + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; >> + >> + return cdns_pcie_read_sz(addr, 0x2); >> } >> >> static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) >> -- >> 2.17.1 >>
TI's J721E SoC uses Cadence PCIe core to implement both RC mode and EP mode. The high level features are: *) Supports Legacy, MSI and MSI-X interrupt *) Supports upto GEN4 speed mode *) Supports SR-IOV *) Supports multiple physical function *) Ability to route all transactions via SMMU This patch series *) Add support in Cadence PCIe core to be used for TI's J721E SoC *) Add a driver for J721E PCIe wrapper v1 of the series can be found @ [1] v2 of the series can be found @ [2] v3 of the series can be found @ [5] v4 of the series can be found @ [6] v5 of the series can be found @ [7] v6 of the series can be found @ [8] Changes from v6: 1) Fixed bot found errors running 'make dt_binding_check' Changes from v5: 1) Added Reviewed-by: for PATCH #6 2) Protect writes to PCI_STATUS with spin_lock during raising interrupts in EP mode to reduce the time between read and write of RMW. Changes from v4: 1) Added Reviewed-by: & Acked-by: tags from RobH 2) Removed un-used accessors for pcie-cadence.h and removed having ops for read/write accessors 3) Updated cdns,cdns-pcie-host.yaml to remove "mem" from reg Changes from v3: 1) Changed the order of files in MAINTAINTERS file to fix Joe's comments 2) Fixed indentation and added Reviewed-by: Rob Herring <robh@kernel.org> 3) Cleaned up computing msix_tbl 4) Fixed RobH's comment on J721E driver Changes from v2: 1) Converting Cadence binding to YAML schema was done as a separate series [3] & [4]. [3] is merged and [4] is pending. 2) Included MSI-X support in this series 3) Added link down interrupt handling (only error message) 4) Rebased to latest 5.7-rc1 5) Adapted TI J721E binding to [3] & [4] Changes from v1: 1) Added DT schemas cdns-pcie-host.yaml, cdns-pcie-ep.yaml and cdns-pcie.yaml for Cadence PCIe core and included it in TI's PCIe DT schema. 2) Added cpu_addr_fixup() for Cadence Platform driver. 3) Fixed subject/description/renamed functions as commented by Andrew Murray. [1] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com [2] -> http://lore.kernel.org/r/20200106102058.19183-1-kishon@ti.com [3] -> http://lore.kernel.org/r/20200305103017.16706-1-kishon@ti.com [4] -> http://lore.kernel.org/r/20200417114322.31111-1-kishon@ti.com [5] -> http://lore.kernel.org/r/20200417125753.13021-1-kishon@ti.com [6] -> http://lore.kernel.org/r/20200506151429.12255-1-kishon@ti.com [7] -> http://lore.kernel.org/r/20200522033631.32574-1-kishon@ti.com [8] -> http://lore.kernel.org/r/20200708093018.28474-1-kishon@ti.com Alan Douglas (1): PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I (13): PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path linux/kernel.h: Add PTR_ALIGN_DOWN macro PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses PCI: cadence: Add support to start link and verify link status PCI: cadence: Allow pci_host_bridge to have custom pci_ops dt-bindings: PCI: cadence: Remove "mem" from reg binding PCI: cadence: Add new *ops* for CPU addr fixup PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC PCI: j721e: Add TI J721E PCIe driver misc: pci_endpoint_test: Add J721E in pci_device_id table MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe .../bindings/pci/cdns,cdns-pcie-host.yaml | 8 +- .../bindings/pci/ti,j721e-pci-ep.yaml | 94 ++++ .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++ MAINTAINERS | 4 +- drivers/misc/pci_endpoint_test.c | 9 + drivers/pci/controller/cadence/Kconfig | 23 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-j721e.c | 493 ++++++++++++++++++ .../pci/controller/cadence/pcie-cadence-ep.c | 129 ++++- .../controller/cadence/pcie-cadence-host.c | 59 ++- .../controller/cadence/pcie-cadence-plat.c | 13 + drivers/pci/controller/cadence/pcie-cadence.c | 8 +- drivers/pci/controller/cadence/pcie-cadence.h | 133 ++++- include/linux/kernel.h | 1 + 14 files changed, 1035 insertions(+), 53 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml create mode 100644 drivers/pci/controller/cadence/pci-j721e.c -- 2.17.1