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[209.132.180.67]) by mx.google.com with ESMTP id k1si9354231pao.142.2014.03.31.08.18.00; Mon, 31 Mar 2014 08:18:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753793AbaCaPRx (ORCPT + 5 others); Mon, 31 Mar 2014 11:17:53 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:58755 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753558AbaCaPRv (ORCPT ); Mon, 31 Mar 2014 11:17:51 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s2VFHS5u021895; Mon, 31 Mar 2014 10:17:28 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2VFHSOi023363; Mon, 31 Mar 2014 10:17:28 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Mon, 31 Mar 2014 10:17:28 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2VFGm46013169; Mon, 31 Mar 2014 10:17:25 -0500 From: Tero Kristo To: , , CC: Subject: [PATCH 19/55] ARM: OMAP3: PRM: remove references to prm-regbits-34xx.h from PRM core code Date: Mon, 31 Mar 2014 18:15:58 +0300 Message-ID: <1396278994-12624-20-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1396278994-12624-1-git-send-email-t-kristo@ti.com> References: <1396278994-12624-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: t-kristo@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Done in preparation to make PRM a standalone driver. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/prm3xxx.c | 54 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index f1d3e15..8ae209a 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -23,10 +23,62 @@ #include "prm3xxx.h" #include "prm2xxx_3xxx_private.h" #include "cm2xxx_3xxx_private.h" -#include "prm-regbits-34xx.h" #include "cm3xxx.h" #include "cm-regbits-34xx.h" +#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) +#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 +#define OMAP3430_GLOBAL_SW_RST_SHIFT 1 +#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 +#define OMAP3430_MPU_WD_RST_SHIFT 4 +#define OMAP3430_SECURE_WD_RST_SHIFT 5 +#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 +#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 +#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 +#define OMAP3430_ICEPICK_RST_SHIFT 9 +#define OMAP3430_ICECRUSHER_RST_SHIFT 10 + +#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) +#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) + +#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) +#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) + +#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) + +#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) +#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) +#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) +#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) +#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) +#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) +#define OMAP3430_GRPSEL_UART3_MASK (1 << 11) +#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) +#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) +#define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15) +#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) +#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) +#define OMAP3630_GRPSEL_UART4_MASK (1 << 18) + +#define OMAP3430_EN_IO_MASK (1 << 8) +#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) +#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) + +#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 + +#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) +#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) +#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) +#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) +#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) + +#define OMAP3430_RST1_IVA2_MASK (1 << 0) +#define OMAP3430_RST2_IVA2_MASK (1 << 1) +#define OMAP3430_RST3_IVA2_MASK (1 << 2) + +#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) +#define OMAP3430_LOGICSTATEST_MASK (1 << 2) + static const struct omap_prcm_irq omap3_prcm_irqs[] = { OMAP_PRCM_IRQ("wkup", 0, 0), OMAP_PRCM_IRQ("io", 9, 1),