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[209.132.180.67]) by mx.google.com with ESMTP id tb3si9594093pab.260.2014.05.05.13.09.58; Mon, 05 May 2014 13:09:58 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752384AbaEEUJz (ORCPT + 6 others); Mon, 5 May 2014 16:09:55 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:40386 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752163AbaEEUJy (ORCPT ); Mon, 5 May 2014 16:09:54 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s45K9W8Q014194; Mon, 5 May 2014 15:09:32 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s45K9W81025152; Mon, 5 May 2014 15:09:32 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Mon, 5 May 2014 15:09:32 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s45K9WE1022790; Mon, 5 May 2014 15:09:32 -0500 Received: from localhost (j-172-22-140-142.vpn.ti.com [172.22.140.142]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s45K9Wt09746; Mon, 5 May 2014 15:09:32 -0500 (CDT) From: Dan Murphy To: , , , CC: Dan Murphy Subject: [RFC] [v2 Patch 4/6] ARM: dts: am4372: Add prcm_resets node Date: Mon, 5 May 2014 15:09:25 -0500 Message-ID: <1399320567-3639-5-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399320567-3639-1-git-send-email-dmurphy@ti.com> References: <1399320567-3639-1-git-send-email-dmurphy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: dmurphy@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add the prcm_resets node to the prcm parent node. Add the am34xx_resets file to define the am34xx reset lines that are handled by this reset framework. Signed-off-by: Dan Murphy --- arch/arm/boot/dts/am4372.dtsi | 7 +++++ arch/arm/boot/dts/am43xx-resets.dtsi | 52 ++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 arch/arm/boot/dts/am43xx-resets.dtsi diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d1f8707..e1ba7ed 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -84,6 +84,12 @@ prcm_clockdomains: clockdomains { }; + + prcm_resets: resets { + #address-cells = <1>; + #size-cells = <1>; + #reset-cells = <1>; + }; }; scrm: scrm@44e10000 { @@ -739,3 +745,4 @@ }; /include/ "am43xx-clocks.dtsi" +/include/ "am43xx-resets.dtsi" diff --git a/arch/arm/boot/dts/am43xx-resets.dtsi b/arch/arm/boot/dts/am43xx-resets.dtsi new file mode 100644 index 0000000..ef338ba --- /dev/null +++ b/arch/arm/boot/dts/am43xx-resets.dtsi @@ -0,0 +1,52 @@ +/* + * Device Tree Source for AM43XX reset data + * + * Copyright (C) 2014 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&prcm_resets { + icss_rstctrl { + reg = <0x810>, + <0x814>; + + icss_reset: icss_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + gfx_rstctrl { + reg = <0x410>, + <0x414>; + + gfx_reset: gfx_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + per_rstctrl { + reg = <0x2010>, + <0x2014>; + + iva_reset: iva_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + device_rstctrl { + reg = <0x4000>, + <0x4004>; + + device_reset: device_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + +};