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(ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5GBOx3w008965; Mon, 16 Jun 2014 06:25:06 -0500 From: Sricharan R To: , , , Subject: [PATCH V3 01/16] irqchip: crossbar: dont use '0' to mark reserved interrupts Date: Mon, 16 Jun 2014 16:53:01 +0530 Message-ID: <1402917796-31574-2-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1402917796-31574-1-git-send-email-r.sricharan@ti.com> References: <1402917796-31574-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140616_042545_509174_A5FD0B8F X-CRM114-Status: GOOD ( 12.05 ) X-Spam-Score: -5.7 (-----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-5.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.152 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [198.47.26.152 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: nm@ti.com, linux@arm.linux.org.uk, jason@lakedaemon.net, tony@atomide.com, rnayak@ti.com, r.sricharan@ti.com, santosh.shilimkar@ti.com, joe@perches.com, tglx@linutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: r.sricharan@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Nishanth Menon Today '0' is actually reserved, but may not be the same in the future. So, use a flag to mark the GIC interrupts that are reserved. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R --- drivers/irqchip/irq-crossbar.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 3d15d16..20105bc 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -17,6 +17,7 @@ #include #define IRQ_FREE -1 +#define IRQ_RESERVED -2 #define GIC_IRQ_START 32 /* @@ -139,7 +140,7 @@ static int __init crossbar_of_init(struct device_node *node) pr_err("Invalid reserved entry\n"); goto err3; } - cb->irq_map[entry] = 0; + cb->irq_map[entry] = IRQ_RESERVED; } } @@ -170,7 +171,7 @@ static int __init crossbar_of_init(struct device_node *node) * reserved irqs. so find and store the offsets once. */ for (i = 0; i < max; i++) { - if (!cb->irq_map[i]) + if (cb->irq_map[i] == IRQ_RESERVED) continue; cb->register_offsets[i] = reserved;