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[209.132.180.67]) by mx.google.com with ESMTP id fb10si1476889pdb.164.2014.07.17.09.46.03; Thu, 17 Jul 2014 09:46:03 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757467AbaGQQqA (ORCPT + 6 others); Thu, 17 Jul 2014 12:46:00 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:34618 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757309AbaGQQp7 (ORCPT ); Thu, 17 Jul 2014 12:45:59 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6HGjZlD021856; Thu, 17 Jul 2014 11:45:35 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6HGjZ25015419; Thu, 17 Jul 2014 11:45:35 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Thu, 17 Jul 2014 11:45:34 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6HGjZfJ023845; Thu, 17 Jul 2014 11:45:35 -0500 Received: from localhost (j-172-22-151-213.vpn.ti.com [172.22.151.213]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s6HGjYt19597; Thu, 17 Jul 2014 11:45:34 -0500 (CDT) From: Dan Murphy To: , , CC: , Dan Murphy Subject: [v3 PATCH 3/6] ARM: dts: am33xx: Add prcm_resets node Date: Thu, 17 Jul 2014 11:45:28 -0500 Message-ID: <1405615531-15649-3-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405615531-15649-1-git-send-email-dmurphy@ti.com> References: <1405615531-15649-1-git-send-email-dmurphy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: dmurphy@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add the prcm_resets node to the prcm parent node. Add the am33xx_resets file to define the am33xx reset lines that are handled by this reset framework. Signed-off-by: Dan Murphy --- v3 - No changes arch/arm/boot/dts/am33xx-resets.dtsi | 42 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/am33xx.dtsi | 7 ++++++ 2 files changed, 49 insertions(+) create mode 100644 arch/arm/boot/dts/am33xx-resets.dtsi diff --git a/arch/arm/boot/dts/am33xx-resets.dtsi b/arch/arm/boot/dts/am33xx-resets.dtsi new file mode 100644 index 0000000..9260626 --- /dev/null +++ b/arch/arm/boot/dts/am33xx-resets.dtsi @@ -0,0 +1,42 @@ +/* + * Device Tree Source for AM33XX reset data + * + * Copyright (C) 2014 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&prcm_resets { + gfx_rstctrl { + reg = <0x1104>, + <0x1114>; + + gfx_reset: gfx_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + per_rstctrl { + reg = <0xD00>, + <0xD0C>; + + iva_reset: iva_reset { + control-bit = <0x04>; + status-bit = <0x10>; + }; + }; + + device_rstctrl { + reg = <0xf00>, + <0xf08>; + + device_reset: device_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 4a4e02d..5cdc8f0 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -117,6 +117,12 @@ prcm_clockdomains: clockdomains { }; + + prcm_resets: resets { + #address-cells = <1>; + #size-cells = <1>; + #reset-cells = <1>; + }; }; scrm: scrm@44e10000 { @@ -834,3 +840,4 @@ }; /include/ "am33xx-clocks.dtsi" +/include/ "am33xx-resets.dtsi"