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[209.132.180.67]) by mx.google.com with ESMTP id t1si3479062pdr.206.2014.09.02.06.57.24 for ; Tue, 02 Sep 2014 06:57:25 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753692AbaIBN5Y (ORCPT + 5 others); Tue, 2 Sep 2014 09:57:24 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:49574 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753200AbaIBN5X (ORCPT ); Tue, 2 Sep 2014 09:57:23 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s82DvGQ9017985; Tue, 2 Sep 2014 08:57:16 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s82DvGBj028459; Tue, 2 Sep 2014 08:57:16 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Tue, 2 Sep 2014 08:57:15 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s82DvAU0003715; Tue, 2 Sep 2014 08:57:14 -0500 From: Roger Quadros To: CC: , , Roger Quadros Subject: [PATCH 2/6] ARM: dts: am437x-gp-evm: Use BCH16 ECC scheme instead of BCH8 Date: Tue, 2 Sep 2014 16:57:03 +0300 Message-ID: <1409666227-20622-3-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1409666227-20622-1-git-send-email-rogerq@ti.com> References: <1409666227-20622-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , am437x-gp-evm uses a NAND chip with page size 4096 bytes and spare area of 225 bytes per page. For such a setup it is preferrable to use BCH16 ECC scheme over BCH8. This also makes it compatible with ROM code ECC scheme so we can boot with NAND after flashing from kernel. Signed-off-by: Roger Quadros Reviewed-by: Pekon Gupta --- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 646a6ea..402249e 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -424,7 +424,7 @@ ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { reg = <0 0 4>; /* device IO registers */ - ti,nand-ecc-opt = "bch8"; + ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>;