From patchwork Tue Oct 18 15:45:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 78088 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp949709qge; Tue, 18 Oct 2016 08:47:02 -0700 (PDT) X-Received: by 10.98.81.199 with SMTP id f190mr1883315pfb.36.1476805622654; Tue, 18 Oct 2016 08:47:02 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c22si36341912pfk.159.2016.10.18.08.47.02; Tue, 18 Oct 2016 08:47:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030260AbcJRPrA (ORCPT + 4 others); Tue, 18 Oct 2016 11:47:00 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:53965 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964890AbcJRPq7 (ORCPT ); Tue, 18 Oct 2016 11:46:59 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u9IFkTEK026754; Tue, 18 Oct 2016 10:46:29 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u9IFkTll030089; Tue, 18 Oct 2016 10:46:29 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Tue, 18 Oct 2016 10:46:28 -0500 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u9IFkJX8006114; Tue, 18 Oct 2016 10:46:27 -0500 From: Tero Kristo To: , , , , CC: Subject: [PATCHv4 03/15] dt-bindings: clock: add omap4 hwmod clock IDs Date: Tue, 18 Oct 2016 18:45:56 +0300 Message-ID: <1476805568-19264-4-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476805568-19264-1-git-send-email-t-kristo@ti.com> References: <1476805568-19264-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add IDs for omap4 hwmod clocks. These are basically register offsets from the beginning of the clockdomain address space. Signed-off-by: Tero Kristo --- include/dt-bindings/clock/ti,omap44xx.h | 116 ++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 include/dt-bindings/clock/ti,omap44xx.h -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/include/dt-bindings/clock/ti,omap44xx.h b/include/dt-bindings/clock/ti,omap44xx.h new file mode 100644 index 0000000..38af57d --- /dev/null +++ b/include/dt-bindings/clock/ti,omap44xx.h @@ -0,0 +1,116 @@ +/* + * TI OMAP4 SoC clock definitions + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_CLOCK_TI_OMAP4_H__ +#define __DT_BINDINGS_CLOCK_TI_OMAP4_H__ + +#define OMAP44XX_MPUSS_MPU 0x20 +#define OMAP44XX_TESLA_DSP 0x20 +#define OMAP44XX_TESLA_MMU_DSP 0x20 +#define OMAP44XX_ABE_L4_ABE 0x20 +#define OMAP44XX_ABE_AESS 0x28 +#define OMAP44XX_ABE_MCPDM 0x30 +#define OMAP44XX_ABE_DMIC 0x38 +#define OMAP44XX_ABE_MCASP 0x40 +#define OMAP44XX_ABE_MCBSP1 0x48 +#define OMAP44XX_ABE_MCBSP2 0x50 +#define OMAP44XX_ABE_MCBSP3 0x58 +#define OMAP44XX_ABE_SLIMBUS1 0x60 +#define OMAP44XX_ABE_TIMER5 0x68 +#define OMAP44XX_ABE_TIMER6 0x70 +#define OMAP44XX_ABE_TIMER7 0x78 +#define OMAP44XX_ABE_TIMER8 0x80 +#define OMAP44XX_ABE_WD_TIMER3 0x88 +#define OMAP44XX_L4_WKUP_L4_WKUP 0x20 +#define OMAP44XX_L4_WKUP_WD_TIMER2 0x30 +#define OMAP44XX_L4_WKUP_GPIO1 0x38 +#define OMAP44XX_L4_WKUP_TIMER1 0x40 +#define OMAP44XX_L4_WKUP_COUNTER_32K 0x50 +#define OMAP44XX_L4_WKUP_KBD 0x78 +#define OMAP44XX_EMU_SYS_DEBUGSS 0x20 +#define OMAP44XX_L3_DSS_DSS_CORE 0x20 +#define OMAP44XX_L3_DSS_DSS_RFBI 0x20 +#define OMAP44XX_L3_DSS_DSS_HDMI 0x20 +#define OMAP44XX_L3_DSS_DSS_DSI2 0x20 +#define OMAP44XX_L3_DSS_DSS_VENC 0x20 +#define OMAP44XX_L3_DSS_DSS_DISPC 0x20 +#define OMAP44XX_L3_DSS_DSS_DSI1 0x20 +#define OMAP44XX_ISS_FDIF 0x28 +#define OMAP44XX_L4_PER_GPIO2 0x60 +#define OMAP44XX_L4_PER_GPIO3 0x68 +#define OMAP44XX_L4_PER_GPIO4 0x70 +#define OMAP44XX_L4_PER_GPIO5 0x78 +#define OMAP44XX_L4_PER_GPIO6 0x80 +#define OMAP44XX_L4_PER_HDQ1W 0x88 +#define OMAP44XX_L4_PER_I2C1 0xa0 +#define OMAP44XX_L4_PER_I2C2 0xa8 +#define OMAP44XX_L4_PER_I2C3 0xb0 +#define OMAP44XX_L4_PER_I2C4 0xb8 +#define OMAP44XX_L4_PER_L4_PER 0xc0 +#define OMAP44XX_L3_GFX_GPU 0x20 +#define OMAP44XX_L3_INIT_HSI 0x38 +#define OMAP44XX_ISS_ISS 0x20 +#define OMAP44XX_L4_PER_MCBSP4 0xe0 +#define OMAP44XX_L4_PER_MCSPI1 0xf0 +#define OMAP44XX_L4_PER_MCSPI2 0xf8 +#define OMAP44XX_L4_PER_MCSPI3 0x100 +#define OMAP44XX_L4_PER_MCSPI4 0x108 +#define OMAP44XX_L4_PER_MMC3 0x120 +#define OMAP44XX_L4_PER_MMC4 0x128 +#define OMAP44XX_L3_INIT_MMC1 0x28 +#define OMAP44XX_L3_INIT_MMC2 0x30 +#define OMAP44XX_L3_INIT_OCP2SCP_USB_PHY 0xe0 +#define OMAP44XX_L4_PER_TIMER10 0x28 +#define OMAP44XX_L4_PER_TIMER11 0x30 +#define OMAP44XX_L4_PER_TIMER2 0x38 +#define OMAP44XX_L4_PER_TIMER3 0x40 +#define OMAP44XX_L4_PER_TIMER4 0x48 +#define OMAP44XX_L4_PER_TIMER9 0x50 +#define OMAP44XX_L4_PER_ELM 0x58 +#define OMAP44XX_L4_PER_SLIMBUS2 0x138 +#define OMAP44XX_L4_PER_UART1 0x140 +#define OMAP44XX_L4_PER_UART2 0x148 +#define OMAP44XX_L4_PER_UART3 0x150 +#define OMAP44XX_L4_PER_UART4 0x158 +#define OMAP44XX_L4_PER_MMC5 0x160 +#define OMAP44XX_L4_AO_SMARTREFLEX_CORE 0x38 +#define OMAP44XX_L4_AO_SMARTREFLEX_IVA 0x30 +#define OMAP44XX_L4_AO_SMARTREFLEX_MPU 0x28 +#define OMAP44XX_L3_INIT_USB_HOST_FS 0xd0 +#define OMAP44XX_L3_INIT_USB_HOST_HS 0x58 +#define OMAP44XX_L3_INIT_USB_OTG_HS 0x60 +#define OMAP44XX_L3_1_L3_MAIN_1 0x20 +#define OMAP44XX_L3_2_L3_MAIN_2 0x20 +#define OMAP44XX_L3_2_GPMC 0x28 +#define OMAP44XX_L3_2_OCMC_RAM 0x30 +#define OMAP44XX_DUCATI_IPU 0x20 +#define OMAP44XX_DUCATI_MMU_IPU 0x20 +#define OMAP44XX_L3_DMA_DMA_SYSTEM 0x20 +#define OMAP44XX_L3_EMIF_DMM 0x20 +#define OMAP44XX_L3_EMIF_EMIF1 0x30 +#define OMAP44XX_L3_EMIF_EMIF2 0x38 +#define OMAP44XX_D2D_C2C 0x20 +#define OMAP44XX_L4_CFG_L4_CFG 0x20 +#define OMAP44XX_L4_CFG_SPINLOCK 0x28 +#define OMAP44XX_L4_CFG_MAILBOX 0x30 +#define OMAP44XX_L3_INSTR_L3_MAIN_3 0x20 +#define OMAP44XX_L3_INSTR_L3_INSTR 0x28 +#define OMAP44XX_L3_INSTR_OCP_WP_NOC 0x40 +#define OMAP44XX_IVAHD_IVA 0x20 +#define OMAP44XX_IVAHD_SL2IF 0x28 +#define OMAP44XX_L3_INIT_USB_TLL_HS 0x68 + +#endif