From patchwork Thu Nov 19 15:44:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 328421 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp524404ils; Thu, 19 Nov 2020 07:46:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJyKpewEiUDZbqp3w5FCvbVVvocXkEITU+9JZPrUyiYOvbh7RlTpyJ+vrV7Bk9XL2dX3g1/E X-Received: by 2002:a17:906:d92c:: with SMTP id rn12mr28868934ejb.472.1605800761576; Thu, 19 Nov 2020 07:46:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605800761; cv=none; d=google.com; s=arc-20160816; b=AyV86+shrhxTbmMya2wMgSJjHU2WJiT923QWcHPveR9QAzxjb/qTwc9vlAxaGwlAcO ZEr+ITJTD/1UvvUtSdx5PtjBw3GXgcR/FbPTrxew78LPVMnK9P/Nd4KotB3KOfqIq1Ih u7Wnaw9VAfFgrxHUrrLhWwjB6nvihQR79PuWw3gQIkGomXpFGmgiNDXeYbDw/T3cM0lc HqtwzJWOrR6Bw0vu8Imzn38X7rBFykpn01lEGb6C2XV8zsNyi4Iqr/m/Zy6FS+P5vhF2 AD8sC+nrzc1OABS3co0Rp37wT7mNglpi9K1uqqg5imIoHWnxmAd50wBJaqLPNtTlpjSg fT+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=K6/+bqPgqxNYeZrn2Alo2UZZh4XfSRrW8f4wwrjH5kA=; b=wcxFMSf3uLTupQm0tXhrzJi4vyUwIr4IM16/RxDukN/yV+CgoWZ/F29DYDRN/Rpav2 r9jj/Vjb8AOuuYwW9AIZ/k4iXEqnkm5OlNdEXKay7+zySbVzMh9k9AXeytLu56Cksp7e PKyqWoyDWCYK20JBgjFggYUD97FCUMljuVcs3IMm1JTZDBReE88Z3WovIuWiYhDfve8N PEOOOCz1tKySJOR16/1a4/zGaFYQg3PdNLeY6nNLbkt34T1PgFLztBF/mKiJp1OZr3wA UPm07yA3KnVdQCz1IYlHE6POCXq27r/zZb9q8LjsXE31cxlT2UTZG4HdSUCcDg1N9Ve9 hWXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mZE3F27s; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bi17si49423edb.582.2020.11.19.07.46.01; Thu, 19 Nov 2020 07:46:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mZE3F27s; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728869AbgKSPpI (ORCPT + 3 others); Thu, 19 Nov 2020 10:45:08 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:50904 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728851AbgKSPpI (ORCPT ); Thu, 19 Nov 2020 10:45:08 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0AJFj67r126863; Thu, 19 Nov 2020 09:45:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605800706; bh=K6/+bqPgqxNYeZrn2Alo2UZZh4XfSRrW8f4wwrjH5kA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mZE3F27smoiz1XoKz2SBeZ1IROk4cxZZCxCUa2HvpA1QOsOjHBa+SAgqD4/8ZD7jr 3PfVBupZE5GpOsZfk6I4urdwGP2huSepsMgDQ+JFU9bzmaOjci7Onoku1dTFknUZ1T o4BZ+GeGEA/7NgGZbgv8UUsDKiHRBqE8Q61dGVko= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0AJFj6Tx090812 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Nov 2020 09:45:06 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 19 Nov 2020 09:45:06 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 09:45:06 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AJFj5dC103354; Thu, 19 Nov 2020 09:45:05 -0600 From: Grygorii Strashko To: Tony Lindgren CC: Sekhar Nori , , Vignesh Raghavendra , , Grygorii Strashko Subject: [PATCH 1/2] ARM: dts: am33xx-l4: add dt node for new cpsw switchdev driver Date: Thu, 19 Nov 2020 17:44:51 +0200 Message-ID: <20201119154452.26961-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201119154452.26961-1-grygorii.strashko@ti.com> References: <20201119154452.26961-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add DT node for the new cpsw switchdev based driver. Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/am33xx-l4.dtsi | 49 ++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index ea20e4bdf040..2dbf7cdc9882 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -751,6 +751,55 @@ phys = <&phy_gmii_sel 2 1>; }; }; + + mac_sw: switch@0 { + compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch"; + reg = <0x0 0x4000>; + ranges = <0 0 0x4000>; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + syscon = <&scm_conf>; + status = "disabled"; + + interrupts = <40 41 42 43>; + interrupt-names = "rx_thresh", "rx", "tx", "misc"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + label = "port1"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 1>; + }; + + cpsw_port2: port@2 { + reg = <2>; + label = "port2"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 1>; + }; + }; + + davinci_mdio_sw: mdio@1000 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x1000 0x100>; + }; + + cpts { + clocks = <&cpsw_cpts_rft_clk>; + clock-names = "cpts"; + }; + }; }; target-module@180000 { /* 0x4a180000, ap 5 10.0 */