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[v12,0/5] Introduce memory interconnect for NVIDIA Tegra SoCs

Message ID 20201228154920.18846-1-digetx@gmail.com
Headers show
Series Introduce memory interconnect for NVIDIA Tegra SoCs | expand

Message

Dmitry Osipenko Dec. 28, 2020, 3:49 p.m. UTC
Add interconnect support to Tegra124 EMC and display controller drivers.

Changelog:

v12: - This is a re-send of the remaining v11 patches [1] that didn't make
       into v5.11 kernel. No code changes.

       [1] https://lore.kernel.org/lkml/20201203192439.16177-1-digetx@gmail.com/

Dmitry Osipenko (5):
  memory: tegra124-emc: Make driver modular
  memory: tegra124-emc: Continue probing if timings are missing in
    device-tree
  memory: tegra124: Support interconnect framework
  drm/tegra: dc: Support memory bandwidth management
  drm/tegra: dc: Extend debug stats with total number of events

 drivers/clk/tegra/Kconfig            |   3 +
 drivers/clk/tegra/Makefile           |   2 +-
 drivers/clk/tegra/clk-tegra124-emc.c |  41 ++-
 drivers/clk/tegra/clk-tegra124.c     |  26 +-
 drivers/clk/tegra/clk.h              |  18 +-
 drivers/gpu/drm/tegra/Kconfig        |   1 +
 drivers/gpu/drm/tegra/dc.c           | 359 +++++++++++++++++++++++++
 drivers/gpu/drm/tegra/dc.h           |  19 ++
 drivers/gpu/drm/tegra/drm.c          |  14 +
 drivers/gpu/drm/tegra/hub.c          |   3 +
 drivers/gpu/drm/tegra/plane.c        | 121 +++++++++
 drivers/gpu/drm/tegra/plane.h        |  15 ++
 drivers/memory/tegra/Kconfig         |   4 +-
 drivers/memory/tegra/tegra124-emc.c  | 377 ++++++++++++++++++++++++---
 drivers/memory/tegra/tegra124.c      |  82 +++++-
 include/linux/clk/tegra.h            |   8 +
 include/soc/tegra/emc.h              |  16 --
 17 files changed, 1038 insertions(+), 71 deletions(-)
 delete mode 100644 include/soc/tegra/emc.h

Comments

Krzysztof Kozlowski Jan. 5, 2021, 5:03 p.m. UTC | #1
On Mon, Dec 28, 2020 at 06:49:18PM +0300, Dmitry Osipenko wrote:
> Now Internal and External memory controllers are memory interconnection
> providers. This allows us to use interconnect API for tuning of memory
> configuration. EMC driver now supports OPPs and DVFS.
> 
> Tested-by: Nicolas Chauvet <kwizart@gmail.com>
> Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  drivers/memory/tegra/Kconfig        |   1 +
>  drivers/memory/tegra/tegra124-emc.c | 320 +++++++++++++++++++++++++++-
>  drivers/memory/tegra/tegra124.c     |  82 ++++++-
>  3 files changed, 391 insertions(+), 12 deletions(-)

Thanks, applied.

Best regards,
Krzysztof
Dmitry Osipenko Jan. 25, 2021, 5:35 p.m. UTC | #2
28.12.2020 18:49, Dmitry Osipenko пишет:
> Display controller (DC) performs isochronous memory transfers, and thus,

> has a requirement for a minimum memory bandwidth that shall be fulfilled,

> otherwise framebuffer data can't be fetched fast enough and this results

> in a DC's data-FIFO underflow that follows by a visual corruption.

> 

> The Memory Controller drivers provide facility for memory bandwidth

> management via interconnect API. Let's wire up the interconnect API

> support to the DC driver in order to fix the distorted display output

> on T30 Ouya, T124 TK1 and other Tegra devices.

> 

> Tested-by: Peter Geis <pgwipeout@gmail.com>

> Tested-by: Nicolas Chauvet <kwizart@gmail.com>

> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>

> ---


Thierry, I'm looking forward to yours review. Only DRM patches are left
unmerged yet in this series.