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[v3,0/5] Update OPP table and add entries for AM62Ax & AM62Px SoCs

Message ID 20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com
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Series Update OPP table and add entries for AM62Ax & AM62Px SoCs | expand

Message

Bryan Brattlof June 21, 2024, 4:39 p.m. UTC
Hello Everyone

This series starts off the process of updating the OPP decoding tables 
to align with the new speed grade schemes for TI's AM62Ax and AM62Px SoC 
families.

Following this update is the updated binding and the OPPv2 entries we 
will be using for the SoC including the 1.4GHz frequency for our 
reference boards when the VDD_CORE allows.

Thanks for reviewing
~Bryan

Signed-off-by: Bryan Brattlof <bb@ti.com>
---
Changes in v3:
- s/calc_efuse/calculated_efusse/ 
- place compatible string alphabetically
- Link to v2: https://lore.kernel.org/r/20240612-ti-opp-updates-v2-0-422b6747a254@ti.com

Changes in v2:
- removed errant DONOTMERGE tag 
- Link to v1: https://lore.kernel.org/r/20240612-ti-opp-updates-v1-0-3551c31d9872@ti.com

---
Bryan Brattlof (5):
      cpufreq: ti: update OPP table for AM62Ax SoCs
      cpufreq: ti: update OPP table for AM62Px SoCs
      dt-bindings: mfd: syscon: add TI's opp table compatible
      DONOTMERGE: arm64: dts: ti: k3-am62p: add in opp tables
      DONOTMERGE: arm64: dts: ti: k3-am62a: add in opp table

 Documentation/devicetree/bindings/mfd/syscon.yaml |  1 +
 arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi       |  5 ++
 arch/arm64/boot/dts/ti/k3-am62a7-sk.dts           |  9 +++
 arch/arm64/boot/dts/ti/k3-am62a7.dtsi             | 51 ++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi       |  6 ++
 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts           |  9 +++
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi             | 47 ++++++++++++
 drivers/cpufreq/ti-cpufreq.c                      | 94 ++++++++++++++++++++++-
 8 files changed, 220 insertions(+), 2 deletions(-)
---
base-commit: eb9c77d3294d119197f6ad2ddbc2adb41922ee4f
change-id: 20240509-ti-opp-updates-19c109ab1354

Best regards,

Comments

Conor Dooley June 22, 2024, 11:49 a.m. UTC | #1
On Fri, Jun 21, 2024 at 11:39:39AM -0500, Bryan Brattlof wrote:
> The JTAG_USER_ID_USERCODE efuse address, which is located inside the
> WKUP_CTRL_MMR0 range holds information to identify the speed grades of
> various components on TI's K3 SoCs. Add a compatible to allow the
> cpufreq driver to obtain the data to limit the maximum frequency for the
> CPUs under Linux control.
> 
> Signed-off-by: Bryan Brattlof <bb@ti.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Viresh Kumar June 25, 2024, 7:18 a.m. UTC | #2
On 21-06-24, 11:39, Bryan Brattlof wrote:
> Hello Everyone
> 
> This series starts off the process of updating the OPP decoding tables 
> to align with the new speed grade schemes for TI's AM62Ax and AM62Px SoC 
> families.
> 
> Following this update is the updated binding and the OPPv2 entries we 
> will be using for the SoC including the 1.4GHz frequency for our 
> reference boards when the VDD_CORE allows.

> Bryan Brattlof (5):
>       cpufreq: ti: update OPP table for AM62Ax SoCs
>       cpufreq: ti: update OPP table for AM62Px SoCs

Applied above patches. Thanks.