| Message ID | 20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org |
|---|---|
| Headers | show |
| Series | drm/msm: adreno: add support for DDR bandwidth scaling via GMU | expand |
On Tue, Nov 19, 2024 at 06:56:38PM +0100, Neil Armstrong wrote: > Now the features defines have the right name, introduce a features > bitfield and move the features defines in it, fixing all code checking > for them. > > No functional changes intended. I think it might be better to squahs this patch into the previous one, it would simplify checking that we use .quirks for ADRENO_QUIRK_foo and .features for ADRENO_FEAT_bar. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 34 +++++++++++++++--------------- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- > drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +++--- > 4 files changed, 24 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 825c820def315968d508973c8ae40c7c7b646569..93f0d4bf50ba773ecde93e6c29a2fcec24ebb7b3 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a615_zap.mbn", > .a6xx = &(const struct a6xx_info) { > @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .a6xx = &(const struct a6xx_info) { > .protect = &a630_protect, > @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a615_zap.mdt", > .a6xx = &(const struct a6xx_info) { > @@ -864,7 +864,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a620_zap.mbn", > @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a630_zap.mdt", > .a6xx = &(const struct a6xx_info) { > @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a640_zap.mdt", > .a6xx = &(const struct a6xx_info) { > @@ -934,7 +934,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M + SZ_128K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a650_zap.mdt", > @@ -961,7 +961,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M + SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a660_zap.mdt", > @@ -981,7 +981,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M + SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .a6xx = &(const struct a6xx_info) { > @@ -1000,7 +1000,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a660_zap.mbn", > @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_2M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a640_zap.mdt", > .a6xx = &(const struct a6xx_info) { > @@ -1046,7 +1046,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_4M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a690_zap.mdt", > @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = SZ_128K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_HW_APRIV, > + .features = ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a702_zap.mbn", > .a6xx = &(const struct a6xx_info) { > @@ -1355,7 +1355,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = SZ_2M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV | > ADRENO_FEAT_PREEMPTION, > .init = a6xx_gpu_init, > @@ -1377,7 +1377,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = 3 * SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV | > ADRENO_FEAT_PREEMPTION, > .init = a6xx_gpu_init, > @@ -1400,7 +1400,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = 3 * SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV | > ADRENO_FEAT_PREEMPTION, > .init = a6xx_gpu_init, > @@ -1422,7 +1422,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = 3 * SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV | > ADRENO_FEAT_PREEMPTION, > .init = a6xx_gpu_init, > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 2ebd3fac212576a1507e0b6afe2560cd0408dd89..654d0cff421f15901cd4bf33b41e70004634ec75 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); > > adreno_gpu->base.hw_apriv = > - !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV); > + !!(config->info->features & ADRENO_FEAT_HAS_HW_APRIV); > > /* gpu->info only gets assigned in adreno_gpu_init() */ > is_a7xx = config->info->family == ADRENO_7XX_GEN1 || > @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > } > > if ((enable_preemption == 1) || (enable_preemption == -1 && > - (config->info->quirks & ADRENO_FEAT_PREEMPTION))) > + (config->info->features & ADRENO_FEAT_PREEMPTION))) > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); > else if (is_a7xx) > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index 09d4569f77528c2a20cabc814668c4c930dd07f1..11a228472fa0cef3b6e4e21a366470fbbc3ea8df 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > > priv->is_a2xx = info->family < ADRENO_3XX; > priv->has_cached_coherent = > - !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT); > + !!(info->features & ADRENO_FEAT_HAS_CACHED_COHERENT); > > gpu = info->init(drm); > if (IS_ERR(gpu)) { > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 8782c25e8a393ec7d9dc23ad450908d039bd08c5..4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -55,9 +55,9 @@ enum adreno_family { > #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) > #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) > > -#define ADRENO_FEAT_HAS_HW_APRIV BIT(3) > -#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4) > -#define ADRENO_FEAT_PREEMPTION BIT(5) > +#define ADRENO_FEAT_HAS_HW_APRIV BIT(0) > +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) > +#define ADRENO_FEAT_PREEMPTION BIT(2) > > /* Helper for formating the chip_id in the way that userspace tools like > * crashdec expect. > @@ -98,6 +98,7 @@ struct adreno_info { > uint32_t revn; > const char *fw[ADRENO_FW_MAX]; > uint32_t gmem; > + u64 features; > u64 quirks; > struct msm_gpu *(*init)(struct drm_device *dev); > const char *zapfw; > > -- > 2.34.1 >
On Tue, Nov 19, 2024 at 06:56:40PM +0100, Neil Armstrong wrote: > The Adreno GMU Management Unit (GMU) can also scale DDR Bandwidth along > the Frequency and Power Domain level, but by default we leave the > OPP core scale the interconnect ddr path. > > In order to calculate vote values used by the GPU Management > Unit (GMU), we need to parse all the possible OPP Bandwidths and > create a vote value to be sent to the appropriate Bus Control > Modules (BCMs) declared in the GPU info struct. > > The vote array will then be used to dynamically generate the GMU > bw_table sent during the GMU power-up. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> LGTM, two minor nits below. > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 153 ++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 14 ++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + > 3 files changed, 168 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 14db7376c712d19446b38152e480bd5a1e0a5198..f6814d92a4edb29ba8a34a34aabb8b2324e9c6a4 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -9,6 +9,7 @@ > #include <linux/pm_domain.h> > #include <linux/pm_opp.h> > #include <soc/qcom/cmd-db.h> > +#include <soc/qcom/tcs.h> > #include <drm/drm_gem.h> > > #include "a6xx_gpu.h" > @@ -1287,6 +1288,109 @@ static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) > return 0; > } > > +/** > + * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM) > + * @unit: divisor used to convert bytes/sec bw value to an RPMh msg > + * @width: multiplier used to convert bytes/sec bw value to an RPMh msg > + * @vcd: virtual clock domain that this bcm belongs to > + * @reserved: reserved field > + */ > +struct bcm_db { > + __le32 unit; > + __le16 width; > + u8 vcd; > + u8 reserved; > +}; > + > +static u64 bcm_div(u64 num, u32 base) > +{ > + /* Ensure that small votes aren't lost. */ > + if (num && num < base) > + return 1; > + > + do_div(num, base); > + > + return num; > +} > + > +static int a6xx_gmu_rpmh_bw_votes_init(const struct a6xx_info *info, > + struct a6xx_gmu *gmu) > +{ > + const struct bcm_db *bcm_data[GMU_MAX_BCMS] = { 0 }; > + unsigned int bcm_index, bw_index; > + > + /* Retrieve BCM data from cmd-db */ > + for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) { > + size_t count; > + > + /* Skip unconfigured BCM */ > + if (!info->bcm[bcm_index].name) > + continue; > + > + bcm_data[bcm_index] = cmd_db_read_aux_data( > + info->bcm[bcm_index].name, > + &count); > + if (IS_ERR(bcm_data[bcm_index])) > + return PTR_ERR(bcm_data[bcm_index]); > + > + if (!count) > + return -EINVAL; > + } > + > + /* Generate BCM votes values for each bandwidth & BCM */ > + for (bw_index = 0; bw_index < gmu->nr_gpu_bws; bw_index++) { > + u32 *data = gmu->gpu_bw_votes[bw_index]; > + u32 bw = gmu->gpu_bw_table[bw_index]; > + > + /* Calculations loosely copied from bcm_aggregate() & tcs_cmd_gen() */ > + for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) { > + bool commit = false; > + u64 peak, vote; > + u16 width; > + u32 unit; > + > + /* Skip unconfigured BCM */ > + if (!info->bcm[bcm_index].name || !bcm_data[bcm_index]) > + continue; Nit: you don't care about the .name anymore, the first check can be dropped. > + > + if (bcm_index == GMU_MAX_BCMS - 1 || > + (bcm_data[bcm_index + 1] && > + bcm_data[bcm_index]->vcd != bcm_data[bcm_index + 1]->vcd)) > + commit = true; > + > + if (!bw) { > + data[bcm_index] = BCM_TCS_CMD(commit, false, 0, 0); > + continue; > + } > + > + if (info->bcm[bcm_index].fixed) { > + u32 perfmode = 0; > + > + if (bw >= info->bcm[bcm_index].perfmode_bw) > + perfmode = info->bcm[bcm_index].perfmode; > + > + data[bcm_index] = BCM_TCS_CMD(commit, true, 0, perfmode); > + continue; > + } > + > + /* Multiply the bandwidth by the width of the connection */ > + width = le16_to_cpu(bcm_data[bcm_index]->width); > + peak = bcm_div((u64)bw * width, info->bcm[bcm_index].buswidth); > + > + /* Input bandwidth value is in KBps, scale the value to BCM unit */ > + unit = le32_to_cpu(bcm_data[bcm_index]->unit); > + vote = bcm_div(peak * 1000ULL, unit); > + > + if (vote > BCM_TCS_CMD_VOTE_MASK) > + vote = BCM_TCS_CMD_VOTE_MASK; > + > + data[bcm_index] = BCM_TCS_CMD(commit, true, vote, vote); > + } > + } > + > + return 0; > +} > + > /* Return the 'arc-level' for the given frequency */ > static unsigned int a6xx_gmu_get_arc_level(struct device *dev, > unsigned long freq) > @@ -1390,12 +1494,15 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > * The GMU votes with the RPMh for itself and on behalf of the GPU but we need > * to construct the list of votes on the CPU and send it over. Query the RPMh > * voltage levels and build the votes > + * The GMU can also vote for DDR interconnects, use the OPP bandwidth entries > + * and BCM parameters to build the votes. > */ > > static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) > { > struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); > struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; > + const struct a6xx_info *info = adreno_gpu->info->a6xx; > struct msm_gpu *gpu = &adreno_gpu->base; > int ret; > > @@ -1407,6 +1514,10 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) > ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, > gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); > > + /* Build the interconnect votes */ > + if (adreno_gpu->info->features & ADRENO_FEAT_GMU_BW_VOTE) > + ret |= a6xx_gmu_rpmh_bw_votes_init(info, gmu); > + > return ret; > } > > @@ -1442,6 +1553,38 @@ static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, > return index; > } > > +static int a6xx_gmu_build_bw_table(struct device *dev, unsigned long *bandwidths, > + u32 size) > +{ > + int count = dev_pm_opp_get_opp_count(dev); > + struct dev_pm_opp *opp; > + int i, index = 0; > + unsigned int bandwidth = 1; > + > + /* > + * The OPP table doesn't contain the "off" bandwidth level so we need to > + * add 1 to the table size to account for it > + */ > + > + if (WARN(count + 1 > size, > + "The GMU bandwidth table is being truncated\n")) > + count = size - 1; > + > + /* Set the "off" bandwidth */ > + bandwidths[index++] = 0; > + > + for (i = 0; i < count; i++) { > + opp = dev_pm_opp_find_bw_ceil(dev, &bandwidth, 0); > + if (IS_ERR(opp)) > + break; > + > + dev_pm_opp_put(opp); > + bandwidths[index++] = bandwidth++; > + } > + > + return index; > +} > + > static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) > { > struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); > @@ -1472,6 +1615,16 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) > > gmu->current_perf_index = gmu->nr_gpu_freqs - 1; > > + /* > + * The GMU also handles GPU Interconnect Votes so build a list > + * of DDR bandwidths from the GPU OPP table > + */ > + if (adreno_gpu->info->features & ADRENO_FEAT_GMU_BW_VOTE) > + gmu->nr_gpu_bws = a6xx_gmu_build_bw_table(&gpu->pdev->dev, > + gmu->gpu_bw_table, ARRAY_SIZE(gmu->gpu_bw_table)); > + > + gmu->current_perf_index = gmu->nr_gpu_freqs - 1; > + > /* Build the list of RPMh votes that we'll send to the GMU */ > return a6xx_gmu_rpmh_votes_init(gmu); > } > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > index b4a79f88ccf45cfe651c86d2a9da39541c5772b3..03603eadc0f9ed866899c95e99f333a511ebc3c1 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > @@ -19,6 +19,16 @@ struct a6xx_gmu_bo { > u64 iova; > }; > > +#define GMU_MAX_BCMS 3 > + > +struct a6xx_bcm { > + char *name; > + unsigned int buswidth; > + bool fixed; > + unsigned int perfmode; > + unsigned int perfmode_bw; > +}; > + > /* > * These define the different GMU wake up options - these define how both the > * CPU and the GMU bring up the hardware > @@ -82,6 +92,10 @@ struct a6xx_gmu { > unsigned long gpu_freqs[16]; > u32 gx_arc_votes[16]; > > + int nr_gpu_bws; > + unsigned long gpu_bw_table[16]; > + u32 gpu_bw_votes[16][GMU_MAX_BCMS]; We still have magic 16 here. GPU_MAX_FREQUENCIES? GPU_FREQ_TABLE_SIZE? > + > int nr_gmu_freqs; > unsigned long gmu_freqs[4]; > u32 cx_arc_votes[4]; > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > index 4aceffb6aae89c781facc2a6e4a82b20b341b6cb..5b80919e595fa1ba0a3afcca55feb89e60870cb1 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > @@ -44,6 +44,7 @@ struct a6xx_info { > u32 gmu_chipid; > u32 gmu_cgc_mode; > u32 prim_fifo_threshold; > + const struct a6xx_bcm bcm[GMU_MAX_BCMS]; > }; > > struct a6xx_gpu { > > -- > 2.34.1 >
On Tue, Nov 19, 2024 at 06:56:44PM +0100, Neil Armstrong wrote: > Now all the DDR bandwidth voting via the GPU Management Unit (GMU) > is in place, declare the Bus Control Modules (BCMs) and the > corresponding parameters in the GPU info struct and add the > GMU_BW_VOTE feature bit to enable it. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 26 ++++++++++++++++++++++++-- > 1 file changed, 24 insertions(+), 2 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Tue, Nov 19, 2024 at 06:56:46PM +0100, Neil Armstrong wrote: > Each GPU OPP requires a specific peak DDR bandwidth, let's add > those to each OPP and also the related interconnect path. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 01ac3769ffa62ffb83c5c51878e2823e1982eb67..331c5140c16bf013190d6da136c0920009d2646b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -2636,6 +2636,9 @@ gpu: gpu@3d00000 { > qcom,gmu = <&gmu>; > #cooling-cells = <2>; > > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; QCOM_ICC_TAG_ALWAYS > + interconnect-names = "gfx-mem"; > + > status = "disabled"; > > zap-shader { > @@ -2649,56 +2652,67 @@ gpu_opp_table: opp-table { > opp-231000000 { > opp-hz = /bits/ 64 <231000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; > + opp-peak-kBps = <2136718>; > }; > > opp-310000000 { > opp-hz = /bits/ 64 <310000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; > + opp-peak-kBps = <6074218>; > }; > > opp-366000000 { > opp-hz = /bits/ 64 <366000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; > + opp-peak-kBps = <6074218>; > }; > > opp-422000000 { > opp-hz = /bits/ 64 <422000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; > + opp-peak-kBps = <8171875>; > }; > > opp-500000000 { > opp-hz = /bits/ 64 <500000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; > + opp-peak-kBps = <8171875>; > }; > > opp-578000000 { > opp-hz = /bits/ 64 <578000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS>; > + opp-peak-kBps = <12449218>; > }; > > opp-629000000 { > opp-hz = /bits/ 64 <629000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; > + opp-peak-kBps = <12449218>; > }; > > opp-680000000 { > opp-hz = /bits/ 64 <680000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; > + opp-peak-kBps = <16500000>; > }; > > opp-720000000 { > opp-hz = /bits/ 64 <720000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; > + opp-peak-kBps = <16500000>; > }; > > opp-770000000 { > opp-hz = /bits/ 64 <770000000>; > opp-level = <RPMH_REGULATOR_LEVEL_NOM>; > + opp-peak-kBps = <16500000>; > }; > > opp-834000000 { > opp-hz = /bits/ 64 <834000000>; > opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; > + opp-peak-kBps = <16500000>; > }; > }; > }; > > -- > 2.34.1 >
The Adreno GMU Management Unit (GMU) can also vote for DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core scale the interconnect ddr path. While scaling the interconnect path was sufficient, newer GPUs like the A750 requires specific vote parameters and bandwidth to achieve full functionnality. In order to get the vote values to be used by the GPU Management Unit (GMU), we need to parse all the possible OPP Bandwidths and create a vote value to be send to the appropriate Bus Control Modules (BCMs) declared in the GPU info struct. The added dev_pm_opp_get_bw() is used in this case. The vote array will then be used to dynamically generate the GMU bw_table sent during the GMU power-up. Those entries will then be used by passing the appropriate bandwidth level when voting for a GPU frequency. This will make sure all resources are equally voted for a same OPP, whatever decision is done by the GMU, it will ensure all resources votes are synchronized. Ran full vulkan-cts-1.3.7.3-0-gd71a36db16d98313c431829432a136dbda692a08 with mesa 25.0.0+git3ecf2a0518 on: - QRD8550 - QRD8650 - HDK8650 Patchset is based on current msm-next including preemption support. Any feedback is welcome. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v2: - opp: rename to dev_pm_opp_get_bw, fix commit message and kerneldoc - remove quirks that are features and move them to a dedicated .features bitfield - get icc bcm kerneldoc, and simplify/cleanup a6xx_gmu_rpmh_bw_votes_init() - no more copies of data - take calculations from icc-rpmh/bcm-voter - move into a single cleaner function - fix a6xx_gmu_set_freq() but not calling dev_pm_opp_set_opp() if !bw_index - also vote for maximum bus bandwidth usage (AB) - overall fix typos in commit messages - Link to v1: https://lore.kernel.org/r/20241113-topic-sm8x50-gpu-bw-vote-v1-0-3b8d39737a9b@linaro.org --- Neil Armstrong (11): opp: core: implement dev_pm_opp_get_bw drm/msm: adreno: rename quirks that are features drm/msm: adreno: move features bits in a separate variable drm/msm: adreno: add GMU_BW_VOTE feature flag drm/msm: adreno: add plumbing to generate bandwidth vote table for GMU drm/msm: adreno: dynamically generate GMU bw table drm/msm: adreno: find bandwidth index of OPP and set it along freq index drm/msm: adreno: request for maximum bus bandwidth usage drm/msm: adreno: enable GMU bandwidth for A740 and A750 arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU arm64: qcom: dts: sm8650: add interconnect and opp-peak-kBps for GPU arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 ++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++ drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 84 ++++++++----- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 181 ++++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 16 ++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 45 ++++++- drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 5 + drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 9 +- drivers/opp/core.c | 25 ++++ include/linux/pm_opp.h | 7 ++ 13 files changed, 358 insertions(+), 46 deletions(-) --- base-commit: 86313a9cd152330c634b25d826a281c6a002eb77 change-id: 20241113-topic-sm8x50-gpu-bw-vote-f5e022fe7a47 Best regards,