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Sat, 3 May 2025 07:04:02 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 3 May 2025 00:03:55 -0700 From: Akhil P Oommen Subject: [PATCH v6 0/7] Support for GPU ACD feature on Adreno X1-85 Date: Sat, 3 May 2025 12:33:31 +0530 Message-ID: <20250503-gpu-acd-v6-0-ab1b52866c64@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAMO/FWgC/2XQS27CMBAG4KtEXtfIM34kZtV7VF2MHQe8IKF2i Foh7l4HBCHKch7fP9JcWQ4phsz21ZWlMMUch74U5qNi/kj9IfDYlpqhQCVqVPxwvnDyLTceWq9 b32kwrGyfU+ji7z3p67vUx5jHIf3dgyeYu88M88qYgAteK5JUd0pJ03z+XKKPvd/54TSHzgIE4 FpA0MECkdXOrMR8d8LXLRAIi8QirUdNBhshnd9KuUiUb1IWKR3V0hgRrKetVE+pBQi7SFWkaEi HjjpFKLdSL1LBm9RFNq0jh1IbG8Ra3h4PT6F0cxwfX2eOcuBlforjvprMDjRPHsv27R8RJ8Rw5 wEAAA== X-Change-ID: 20240724-gpu-acd-6c1dc5dcf516 To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen , Bjorn Andersson , "Maya Matuszczyk" , Anthony Ruhier , Dmitry Baryshkov CC: , , , , , , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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At high level, following are the sequences required for ACD feature: 1. Identify the ACD level data for each regulator corner 2. Send a message to AOSS to switch voltage plan 3. Send a table with ACD level information to GMU during every gpu wake up For (1), it is better to keep ACD level data in devicetree because this value depends on the process node, voltage margins etc which are chipset specific. For instance, same GPU HW IP on a different chipset would have a different set of values. So, a new schema which extends opp-v2 is created to add a new property called "qcom,opp-acd-level". ACD support is dynamically detected based on the presence of "qcom,opp-acd-level" property in GPU's opp table. Also, qmp node should be present under GMU node in devicetree for communication with AOSS. The devicetree patch in this series adds the acd-level data for X1-85 GPU present in Snapdragon X1 Elite chipset. The last two devicetree patches are for Bjorn and all the rest for Rob Clark. --- Changes in v6: - Captured code-review trailers - Link to v5: https://lore.kernel.org/r/20250419-gpu-acd-v5-0-8dbab23569e0@quicinc.com Changes in v5: - Rebased on top of 6.15-rc2 - Move 'acd data fix' mentioned in the prev revision to the correct patch - Make module-param sysfs node read-only (Konrad) - Apply opp-v2-qcom-adreno schema only on adreno opp table - Link to v4: https://lore.kernel.org/r/20250109-gpu-acd-v4-0-08a5efaf4a23@quicinc.com Changes in v4: - Send correct acd data via hfi (Neil) - Fix dt-bindings error - Fix IB vote for the 1.1Ghz OPP - New patch#2 to fix the HFI timeout error seen when ACD is enabled - Link to v3: https://lore.kernel.org/r/20241231-gpu-acd-v3-0-3ba73660e9ca@quicinc.com Changes in v3: - Rebased on top of v6.13-rc4 since X1E doesn't boot properly with msm-next - Update patternProperties regex (Krzysztof) - Update MAINTAINERS file include the new opp-v2-qcom-adreno.yaml - Update the new dt properties' description - Do not move qmp_get() to acd probe (Konrad) - New patches: patch#2, #3 and #6 - Link to v2: https://lore.kernel.org/r/20241021-gpu-acd-v2-0-9c25a62803bc@quicinc.com Changes in v2: - Removed RFC tag for the series - Improve documentation for the new dt bindings (Krzysztof) - Add fallback compatible string for opp-table (Krzysztof) - Link to v1: https://lore.kernel.org/r/20241012-gpu-acd-v1-0-1e5e91aa95b6@quicinc.com --- Akhil P Oommen (7): drm/msm/adreno: Add support for ACD drm/msm/a6xx: Increase HFI response timeout drm/msm: a6x: Rework qmp_get() error handling drm/msm/adreno: Add module param to disable ACD dt-bindings: opp: Add v2-qcom-adreno vendor bindings arm64: dts: qcom: x1e80100: Add ACD levels for GPU arm64: dts: qcom: x1e80100: Add OPPs up to Turbo L3 for GPU .../bindings/opp/opp-v2-qcom-adreno.yaml | 96 ++++++++++++++++++++++ MAINTAINERS | 1 + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 +++++- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 96 +++++++++++++++++++--- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 38 ++++++++- drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21 +++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 4 + 8 files changed, 269 insertions(+), 15 deletions(-) --- base-commit: 8a834b0ac9ceb354a6e0b8cf5b363edca8221bdd change-id: 20240724-gpu-acd-6c1dc5dcf516 Best regards,