From patchwork Fri Oct 23 08:24:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 286742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2340C56202 for ; Fri, 23 Oct 2020 08:25:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 99EAD22210 for ; Fri, 23 Oct 2020 08:25:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="oLXc/imY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S460582AbgJWIZ0 (ORCPT ); Fri, 23 Oct 2020 04:25:26 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54300 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S460535AbgJWIZP (ORCPT ); Fri, 23 Oct 2020 04:25:15 -0400 X-UUID: 1980161871ce45309552688f71154944-20201023 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jUKvU/HzCuL2PPK0da8gu19V+NdKcPP0gYDYa+SwXrM=; b=oLXc/imYIxdZ4AZKP6NZ7gJz4z1l91xCXtsjN4qAlDXT4dTafm45S/AY3g7u0OnFamR2eqEQkoKWnA1SlXc6T14Qyut+JcJzSXReox+my2mAWheBlu4zdHZ4fFBLZtVyxAHcY37PHG+SX+ZEDcjBYHmFjGxyrLJ2p14yiL+5fag=; X-UUID: 1980161871ce45309552688f71154944-20201023 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 358697557; Fri, 23 Oct 2020 16:25:01 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 16:24:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 16:24:59 +0800 From: Hector Yuan To: , , , Rob Herring , "Rafael J. Wysocki" , Viresh Kumar , Maxime Ripard , Santosh Shilimkar , Amit Kucheria , Stephen Boyd , Ulf Hansson , Dave Gerlach , Florian Fainelli , Robin Murphy , Lorenzo Pieralisi , CC: , , Subject: [PATCH v1 5/6] cpufreq: mediatek-hw: Add SVS CPU initialization Date: Fri, 23 Oct 2020 16:24:52 +0800 Message-ID: <1603441493-18554-6-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Use pm_qos to block cpu-idle state for SVS initializing. CPUs must be in power on state when doing SVS. Add polling ack while coufreq hw is ready.(SVS init done) Signed-off-by: Hector.Yuan --- drivers/cpufreq/mediatek-cpufreq-hw.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 1.7.9.5 diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c index 241d93f..15fba20 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -7,20 +7,27 @@ #include #include #include +#include #include #include #include #include +#include #include #define LUT_MAX_ENTRIES 32U #define LUT_FREQ GENMASK(11, 0) #define LUT_ROW_SIZE 0x4 +#define CPUFREQ_HW_STATUS BIT(0) +#define SVS_HW_STATUS BIT(1) +#define POLL_USEC 1000 +#define TIMEOUT_USEC 300000 enum { REG_FREQ_LUT_TABLE, REG_FREQ_ENABLE, REG_FREQ_PERF_STATE, + REG_FREQ_HW_STATE, REG_EM_POWER_TBL, REG_ARRAY_SIZE, @@ -37,6 +44,7 @@ struct cpufreq_mtk { [REG_FREQ_LUT_TABLE] = 0x0, [REG_FREQ_ENABLE] = 0x84, [REG_FREQ_PERF_STATE] = 0x88, + [REG_FREQ_HW_STATE] = 0x8c, [REG_EM_POWER_TBL] = 0x3D0, }; @@ -89,6 +97,12 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct cpufreq_mtk *c; struct device *cpu_dev; struct em_data_callback em_cb = EM_DATA_CB(mtk_cpufreq_get_cpu_power); + struct pm_qos_request *qos_request; + int sig, pwr_hw = CPUFREQ_HW_STATUS | SVS_HW_STATUS; + + qos_request = kzalloc(sizeof(*qos_request), GFP_KERNEL); + if (!qos_request) + return -ENOMEM; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -107,11 +121,29 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) policy->freq_table = c->table; policy->driver_data = c; + /* Let CPUs leave idle-off state for SVS CPU initializing */ + cpu_latency_qos_add_request(qos_request, 0); + /* HW should be in enabled state to proceed now */ writel_relaxed(0x1, c->reg_bases[REG_FREQ_ENABLE]); + if (readl_poll_timeout(c->reg_bases[REG_FREQ_HW_STATE], sig, + (sig & pwr_hw) == pwr_hw, POLL_USEC, + TIMEOUT_USEC)) { + if (!(sig & CPUFREQ_HW_STATUS)) { + pr_info("cpufreq hardware of CPU%d is not enabled\n", + policy->cpu); + return -ENODEV; + } + + pr_info("SVS of CPU%d is not enabled\n", policy->cpu); + } + em_dev_register_perf_domain(cpu_dev, c->nr_opp, &em_cb, policy->cpus); + cpu_latency_qos_remove_request(qos_request); + kfree(qos_request); + return 0; }