From patchwork Sun Dec 27 10:54:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 352585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E247C433E9 for ; Sun, 27 Dec 2020 10:56:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 44B4D224B8 for ; Sun, 27 Dec 2020 10:56:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726182AbgL0Kz5 (ORCPT ); Sun, 27 Dec 2020 05:55:57 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:47759 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726156AbgL0Kz4 (ORCPT ); Sun, 27 Dec 2020 05:55:56 -0500 X-UUID: 5a988252da3145f5a3d23bd1d3a93067-20201227 X-UUID: 5a988252da3145f5a3d23bd1d3a93067-20201227 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1350880203; Sun, 27 Dec 2020 18:55:10 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 27 Dec 2020 18:55:08 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 27 Dec 2020 18:56:16 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd , Philipp Zabel CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Nishanth Menon , Roger Lu , , , , , Subject: [PATCH v10 2/7] [v10, 2/7]: arm64: dts: mt8183: add svs device information Date: Sun, 27 Dec 2020 18:54:44 +0800 Message-ID: <20201227105449.11452-3-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201227105449.11452-1-roger.lu@mediatek.com> References: <20201227105449.11452-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: BAC2FF0050AB195E418ABA2768031E9D913225DFC97EC9EB1CF9A891A0A5323C2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org add compitable/reg/irq/clock/efuse setting in svs node Signed-off-by: Roger Lu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 9cfd961c45eb..b017eb7fbf2a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -479,6 +479,18 @@ status = "disabled"; }; + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", + "t-calibration-data"; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8183-i2c"; reg = <0 0x1100f000 0 0x1000>, @@ -724,6 +736,14 @@ compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; reg = <0 0x11f10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + thermal_calibration: calib@180 { + reg = <0x180 0xc>; + }; + svs_calibration: calib@580 { + reg = <0x580 0x64>; + }; }; u3phy: usb-phy@11f40000 {