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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id e9sm8296888wrg.60.2022.02.06.05.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 05:58:15 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Lukasz Luba , Alim Akhtar , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 4/8] dt-bindings: memory: lpddr3: adjust IO width to spec Date: Sun, 6 Feb 2022 14:58:03 +0100 Message-Id: <20220206135807.211767-5-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> References: <20220206135807.211767-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only 16- and 32-bit IO width. Drop the unsupported others. Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index e36f3607e25a..d6787b5190ee 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -34,10 +34,8 @@ properties: description: | IO bus width in bits of SDRAM chip. enum: - - 64 - 32 - 16 - - 8 manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32