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Wysocki" , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , Perry Yuan , Jassmine Meng , Borislav Petkov , Peter Zijlstra , Ingo Molnar , Viresh Kumar , Steven Rostedt , "Giovanni Gherdovich" , , Huang Rui Subject: [PATCH RESEND v6 3/9] cpupower: Initial AMD P-State capability Date: Wed, 16 Feb 2022 15:35:52 +0800 Message-ID: <20220216073558.751071-4-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220216073558.751071-1-ray.huang@amd.com> References: <20220216073558.751071-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 525bbadb-4015-44a5-feb0-08d9f11f14d7 X-MS-TrafficTypeDiagnostic: MWHPR12MB1888:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1923; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3ssn24aA9FmP5dE+vpi3SAmgImkA7xRgJg2Xj7JV7Ubf2Oa6ZmDt3pd/9HbRq+OWKBzqen+YqeW2pBzBjRgVjdsxrM1F8eRDpdsCEZQDhf5x8Y/YwGFl1Pqhd48H51s7J/bP/HFFg4YOwho6Y9BBLVqu+lS5XHwEGMYOkRmxDPj2s5dG/tYaoED4GPgptJvo+a3Db3LgMNxNVCtLKRbcYxgqHnQ1kUN5Xp/6CmvqeFLd0cre51S0VJkwjZymCYPOoX5vmcNNKJXFZCKZsBd9iCW7F4U2nw6XDAqPPU39U/YEwUd1swgF+By5Umh+RQ1X9F5zOFnjY0mYdFt+02vo1bWwox/GWgfi5uUO/zvnEMnKDguEnOV0sU9JA/p9w7SAmJD+0nUjtP/FbbY9MkqkShUYmabLSqjP0oR7Zm9lgTfaY2Fu3b0BwpjkztIgKGEaDzdUpsH3gr26tAVtgvf+d9ZxWpZ5kiCyIuABDKQNGrestSe5ACr/QwU1xgBCYxlC1WoSklZzsaXYC8j/hp+TdqtRfskCuO3klu0gTeiyFKaJ11WW+nm8d7WE4h41RKOC40MUoppdu5HyQrio7hhqBrg/mxB3h8fBIRHQMOKIlL84BX6HmKJNMSezzzq5w06lbDyrwBQePqxVoNbF8oQssNKqeM4kgNzhxMDNfZLST5BBmQPawwQnSzWi8DAtz5hZNYgpncmJZ9e4PXaTT01RvA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(70586007)(110136005)(4326008)(7416002)(54906003)(356005)(8936002)(316002)(5660300002)(70206006)(2906002)(8676002)(16526019)(186003)(508600001)(36860700001)(6666004)(26005)(1076003)(2616005)(336012)(86362001)(7696005)(47076005)(40460700003)(36756003)(426003)(82310400004)(81166007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2022 07:36:44.4990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 525bbadb-4015-44a5-feb0-08d9f11f14d7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1888 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org If kernel starts the AMD P-State module, the cpupower will initial the capability flag as CPUPOWER_CAP_AMD_PSTATE. And once AMD P-State capability is set, it won't need to set legacy ACPI relative capabilities anymore. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/cpuid.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/cpuid.c b/tools/power/cpupower/utils/helpers/cpuid.c index 72eb43593180..eae91f11d187 100644 --- a/tools/power/cpupower/utils/helpers/cpuid.c +++ b/tools/power/cpupower/utils/helpers/cpuid.c @@ -149,6 +149,19 @@ int get_cpu_info(struct cpupower_cpu_info *cpu_info) if (ext_cpuid_level >= 0x80000008 && cpuid_ebx(0x80000008) & (1 << 4)) cpu_info->caps |= CPUPOWER_CAP_AMD_RDPRU; + + if (cpupower_amd_pstate_enabled()) { + cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATE; + + /* + * If AMD P-State is enabled, the firmware will treat + * AMD P-State function as high priority. + */ + cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB_MSR; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_HW_PSTATE; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_PSTATEDEF; + } } if (cpu_info->vendor == X86_VENDOR_INTEL) {