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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id z22-20020a7bc156000000b003942a244f30sm3047819wmi.9.2022.05.12.05.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 05:24:44 -0700 (PDT) From: Alexandre Bailon To: robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de Cc: rafael@kernel.org, daniel.lezcano@linaro.org, amitk@kernel.org, rui.zhang@intel.com, michael.kao@mediatek.com, ben.tseng@mediatek.com, ethan.chang@mediatek.com, frank-w@public-files.de, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, khilman@baylibre.com, Tinghan Shen , Alexandre Bailon Subject: [PATCH v6 7/7] arm64: dts: mt8195: Add thermal zone Date: Thu, 12 May 2022 14:24:33 +0200 Message-Id: <20220512122433.1399802-8-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512122433.1399802-1-abailon@baylibre.com> References: <20220512122433.1399802-1-abailon@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Tinghan Shen This adds the thermal zone for the mt8195. Signed-off-by: Tinghan Shen Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 103 +++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 12887fb4d0d1..d6e5b595a89f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -823,6 +823,21 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts: lvts@1100b000 { + compatible = "mediatek,mt8195-lvts"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100b000 0 0x1000>, + <0 0x11278000 0 0x1000>; + interrupts = , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names = "lvts_clk"; + resets = <&infracfg_rst 1>, + <&infracfg_rst 2>; + nvmem-cells = <&lvts_e_data1 &lvts_e_data2>; + nvmem-cell-names = "e_data1","e_data2"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1627,4 +1642,92 @@ vencsys_core1: clock-controller@1b000000 { #clock-cells = <1>; }; }; + + thermal_zones: thermal-zones { + cpu_big1 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 0>; + }; + cpu_big2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 1>; + }; + cpu_big3 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 2>; + }; + cpu_big4 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 3>; + }; + cpu_little1{ + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 4>; + }; + cpu_little2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 5>; + }; + cpu_little3 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 6>; + }; + cpu_little4 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 7>; + }; + vpu1 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 8>; + }; + vpu2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 9>; + }; + gpu1 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 10>; + }; + gpu2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 11>; + }; + vdec { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 12>; + }; + img { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 13>; + }; + infra { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 14>; + }; + cam1 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 15>; + }; + cam2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 16>; + }; + }; };