Message ID | 20221202162353.274009-1-marex@denx.de |
---|---|
State | Accepted |
Commit | 8848c0d7a0782c263a7827697d5acfcc09a19a5f |
Headers | show |
Series | [v3,1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells | expand |
On 02/12/2022 17:23, Marek Vasut wrote: > The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with > calibration values from OCOTP. Document optional phandle to OCOTP nvmem > provider. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Marek Vasut <marex@denx.de> > Applied, thanks
diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml index 89c54e08ee61b..b90726229ac9c 100644 --- a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml @@ -32,6 +32,13 @@ properties: clocks: maxItems: 1 + nvmem-cells: + maxItems: 1 + description: Phandle to the calibration data provided by ocotp + + nvmem-cell-names: + const: calib + "#thermal-sensor-cells": description: | Number of cells required to uniquely identify the thermal