From patchwork Tue Dec 13 22:43:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 634099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 552FDC4332F for ; Tue, 13 Dec 2022 22:43:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235907AbiLMWnj (ORCPT ); Tue, 13 Dec 2022 17:43:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236733AbiLMWnh (ORCPT ); Tue, 13 Dec 2022 17:43:37 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DA98722292; Tue, 13 Dec 2022 14:43:35 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,242,1665414000"; d="scan'208";a="143229837" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2022 07:43:35 +0900 Received: from mulinux.home (unknown [10.226.93.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 819BB40F4527; Wed, 14 Dec 2022 07:43:30 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH 3/5] dt-bindings: mfd: Add RZ/V2M PWC global registers bindings Date: Tue, 13 Dec 2022 22:43:08 +0000 Message-Id: <20221213224310.543243-4-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> References: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The RZ/V2M PWC is a multi-function device, and its software support relies on "syscon" and "simple-mfd". Add the dt-bindings for the top level device tree node. Signed-off-by: Fabrizio Castro --- .../bindings/mfd/renesas,rzv2m-pwc.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml new file mode 100644 index 000000000000..a7e180bfbd83 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/renesas,rzv2m-pwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with the below + capabilities + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + - general-purpose output pins + +maintainers: + - Fabrizio Castro + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc # RZ/V2M + - renesas,r9a09g055-pwc # RZ/V2MA + - const: renesas,rzv2m-pwc + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + gpio: + type: object + $ref: /schemas/gpio/renesas,rzv2m-pwc-gpio.yaml# + description: General-Purpose Output pins controller. + + poweroff: + type: object + $ref: /schemas/power/reset/renesas,rzv2m-pwc-poweroff.yaml# + description: Power OFF controller. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pwc: pwc@a3700000 { + compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc", "syscon", + "simple-mfd"; + reg = <0xa3700000 0x800>; + + gpio { + compatible = "renesas,r9a09g011-pwc-gpio", + "renesas,rzv2m-pwc-gpio"; + regmap = <&pwc>; + offset = <0x80>; + gpio-controller; + #gpio-cells = <2>; + }; + + poweroff { + compatible = "renesas,r9a09g011-pwc-poweroff", + "renesas,rzv2m-pwc-poweroff"; + regmap = <&pwc>; + }; + };