From patchwork Tue Apr 11 08:32:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Huo X-Patchwork-Id: 672567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 868C1C77B76 for ; Tue, 11 Apr 2023 08:33:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230467AbjDKIdF convert rfc822-to-8bit (ORCPT ); Tue, 11 Apr 2023 04:33:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230459AbjDKIdD (ORCPT ); Tue, 11 Apr 2023 04:33:03 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F491E62; Tue, 11 Apr 2023 01:33:02 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 1910C24E29A; Tue, 11 Apr 2023 16:33:01 +0800 (CST) Received: from EXMBX067.cuchost.com (172.16.6.67) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 16:33:01 +0800 Received: from localhost.localdomain (113.72.145.176) by EXMBX067.cuchost.com (172.16.6.67) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 16:33:00 +0800 From: Mason Huo To: "Rafael J. Wysocki" , Viresh Kumar , Emil Renner Berthing , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou CC: Shengyu Qu , , , , , Mason Huo Subject: [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Date: Tue, 11 Apr 2023 16:32:57 +0800 Message-ID: <20230411083257.16155-4-mason.huo@starfivetech.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411083257.16155-1-mason.huo@starfivetech.com> References: <20230411083257.16155-1-mason.huo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX067.cuchost.com (172.16.6.67) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. It supports up to 4 cpu frequency loads. Signed-off-by: Mason Huo --- .../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index df582bddae4b..ae446b268e78 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -228,3 +228,28 @@ &uart0 { pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&U74_1 { + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + cpu-supply = <®_dcdc2>; +}; + +&U74_2 { + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + cpu-supply = <®_dcdc2>; +}; + +&U74_3 { + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + cpu-supply = <®_dcdc2>; +}; + +&U74_4 { + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + cpu-supply = <®_dcdc2>; +}; + diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..c867f968d054 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -53,6 +53,7 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -79,6 +80,7 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,6 +107,7 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -131,6 +134,7 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -164,6 +168,27 @@ core4 { }; }; + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin";