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Tue, 18 Apr 2023 04:36:12 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 18 Apr 2023 04:36:11 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Tue, 18 Apr 2023 04:36:07 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , , , , , , , Subject: [Patch 5/6] arm64: cpufeature: Export get_cpu_with_amu_feat func Date: Tue, 18 Apr 2023 17:04:58 +0530 Message-ID: <20230418113459.12860-6-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418113459.12860-1-sumitg@nvidia.com> References: <20230418113459.12860-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT033:EE_|PH8PR12MB6914:EE_ X-MS-Office365-Filtering-Correlation-Id: 1831378e-dd9b-4a39-b9e7-08db40011df0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199021)(46966006)(36840700001)(40470700004)(36756003)(4326008)(110136005)(54906003)(316002)(70586007)(70206006)(7696005)(478600001)(6666004)(41300700001)(5660300002)(82310400005)(8676002)(8936002)(40480700001)(2906002)(7416002)(4744005)(34020700004)(82740400003)(86362001)(356005)(426003)(2616005)(336012)(107886003)(40460700003)(1076003)(26005)(186003)(36860700001)(47076005)(7636003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 11:36:14.3267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1831378e-dd9b-4a39-b9e7-08db40011df0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6914 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Export the get_cpu_with_amu_feat() function for use by "cppc_cpufreq" to check if any CPU implements ARM's Activity Monitor Unit (AMU). If AMU is available, then for re-constructing the current CPU freq from its counters, queue work on target CPU to read the counters in a single call instead of reading them in separate smp calls. Signed-off-by: Sumit Gupta --- arch/arm64/kernel/cpufeature.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d9345e9c0226..ec31da7043eb 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1917,6 +1917,7 @@ int get_cpu_with_amu_feat(void) { return cpumask_any(&amu_cpus); } +EXPORT_SYMBOL_GPL(get_cpu_with_amu_feat); static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) {