From patchwork Tue Jun 13 04:24:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 692446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78C21C77B7A for ; Tue, 13 Jun 2023 04:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239649AbjFMEZu (ORCPT ); Tue, 13 Jun 2023 00:25:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239412AbjFMEZF (ORCPT ); Tue, 13 Jun 2023 00:25:05 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFD7E294F; Mon, 12 Jun 2023 21:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686630159; x=1718166159; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=kkx8+i7/ujXbIWdrAp+zwYJqUDlBUvhBgxYJWBRnjXc=; b=LCZYlE7YCGhLrx8+gTEekjH/iUW6Fl8f6LFKw/Cf4wmSbr/rGgnR0G93 y3rIK9nc8bwPZroUcpO1SO6Fq/8rO05NrpKhBrI418PGmd5TCOG6HGPUS +mFNwnmC8ZZgYdz8CyZc5Zo8mSyHPFB0MgDnX1mIdMCK/vCPcks1aImrK eSsoJyubC8VhWD95szP6QcAwCug0FrQQl6QNfA8cs2Tio9V8oq9NnZal4 OaI/MDOblMD2p8fC+Ma+hq2Y6TOP2X2X6/V/sJRfHzRata0k035ySCxR4 fWKmGilb9Esw+WEVovZARaHNI6ITrHetEoxwub6JCgxGHLwr2oZYpuZwM A==; X-IronPort-AV: E=McAfee;i="6600,9927,10739"; a="358222277" X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="358222277" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2023 21:22:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10739"; a="661854998" X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="661854998" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga003.jf.intel.com with ESMTP; 12 Jun 2023 21:22:01 -0700 From: Ricardo Neri To: "Peter Zijlstra (Intel)" , Juri Lelli , Vincent Guittot Cc: Ricardo Neri , "Ravi V. Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , Lukasz Luba , Ionela Voinescu , Zhao Liu , "Yuan, Perry" , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" , Zhao Liu Subject: [PATCH v4 21/24] x86/sched/ipcc: Implement model-specific checks for task classification Date: Mon, 12 Jun 2023 21:24:19 -0700 Message-Id: <20230613042422.5344-22-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230613042422.5344-1-ricardo.neri-calderon@linux.intel.com> References: <20230613042422.5344-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In Alder Lake and Raptor Lake, the result of thread classification is more accurate when only one SMT sibling is busy. Classification results for class 2 and 3 are always reliable. Changing the classification of a task too frequently may lead to unnecessary migrations. Only update the class of a task if it is considered accurate and has been constant during four consecutive user ticks. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Ionela Voinescu Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Lukasz Luba Cc: Mel Gorman Cc: Perry Yuan Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: Zhao Liu Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v3: * Relocated this code to arch/x86/kernel/sched_ipcc.c (Rafael) Changes since v2: * None Changes since v1: * Adjusted the result the classification of Intel Thread Director to start at class 1. Class 0 for the scheduler means that the task is unclassified. * Used the new names of the IPC classes members in task_struct. * Reworked helper functions to use sched_smt_siblings_idle() to query the idle state of the SMT siblings of a CPU. --- arch/x86/kernel/sched_ipcc.c | 60 +++++++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/sched_ipcc.c b/arch/x86/kernel/sched_ipcc.c index 685e7b3b5375..dd73fc8be49b 100644 --- a/arch/x86/kernel/sched_ipcc.c +++ b/arch/x86/kernel/sched_ipcc.c @@ -18,11 +18,67 @@ #include +#include #include +#define CLASS_DEBOUNCER_SKIPS 4 + +/** + * debounce_and_update_class() - Process and update a task's classification + * + * @p: The task of which the classification will be updated + * @new_ipcc: The new IPC classification + * + * Update the classification of @p with the new value that hardware provides. + * Only update the classification of @p if it has been the same during + * CLASS_DEBOUNCER_SKIPS consecutive ticks. + */ +static void debounce_and_update_class(struct task_struct *p, u8 new_ipcc) +{ + u16 debounce_skip; + + /* The class of @p changed. Only restart the debounce counter. */ + if (p->ipcc_tmp != new_ipcc) { + p->ipcc_cntr = 1; + goto out; + } + + /* + * The class of @p did not change. Update it if it has been the same + * for CLASS_DEBOUNCER_SKIPS user ticks. + */ + debounce_skip = p->ipcc_cntr + 1; + if (debounce_skip < CLASS_DEBOUNCER_SKIPS) + p->ipcc_cntr++; + else + p->ipcc = new_ipcc; + +out: + p->ipcc_tmp = new_ipcc; +} + +static bool classification_is_accurate(u8 hfi_class, bool smt_siblings_idle) +{ + switch (boot_cpu_data.x86_model) { + case INTEL_FAM6_ALDERLAKE: + case INTEL_FAM6_ALDERLAKE_L: + case INTEL_FAM6_RAPTORLAKE: + case INTEL_FAM6_RAPTORLAKE_P: + case INTEL_FAM6_RAPTORLAKE_S: + if (hfi_class == 3 || hfi_class == 2 || smt_siblings_idle) + return true; + + return false; + + default: + return false; + } +} + void intel_update_ipcc(struct task_struct *curr) { u8 hfi_class; + bool idle; if (intel_hfi_read_classid(&hfi_class)) return; @@ -31,5 +87,7 @@ void intel_update_ipcc(struct task_struct *curr) * 0 is a valid classification for Intel Thread Director. A scheduler * IPCC class of 0 means that the task is unclassified. Adjust. */ - curr->ipcc = hfi_class + 1; + idle = sched_smt_siblings_idle(task_cpu(curr)); + if (classification_is_accurate(hfi_class, idle)) + debounce_and_update_class(curr, hfi_class + 1); }