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Wysocki" , Viresh Kumar , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: Vibhore Vardhan , , , , , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2681; i=bb@ti.com; h=from:subject:message-id; bh=OnjgNJDFxiPKZgZGyPgGQPGW1SV4Zx/0dKqTvtZJ1N0=; b=owNCWmg5MUFZJlNZoUljNAAAaf////7ffrt3/n7+9tJvXzSOr9t39b5//cs3fL/7yfbZ/++wA Rs2gxQAA0AyPUDQAAMgaAZABoABoAAGQDQ0B6gA2oNMQAGjQPU009EbTJqIAaaDQDQyZAaAAAxq ZNND1AGgGTTQGQZDCG1D0IDQ0aBkMgaA0eoDQGgBgyg000aDEaADTJiaNA00MhoAA0wgGQDJhBo AyAA0MTQAaBpo0GajRoyZMgAQJzh5Sv10QZIFFR1dBizrHgGlWSJ/JQGj0FiiZG1OC04yJAGFO5 4yg7PVk6cFz5DoGuqyi2ep/UtqoAhw/jpLtQWuDNVcsPHlzzGJYLKzD2QhAhSXem8b3qFyQloir MFGBZAPeo8CZvshdRcwnPC/zt88nwCYA+rFCIEyjDRoPuDXEsJuyRrOM2JZc3rxpOKWGSlH0JaN vwtTfUG0kCE2FwG9QmOLDh9UpJHx85Hu6S4ZOn4SAvCm8aIrmAqnxws+ncwD5ELNlgOyXLVRn8z y5LDvkg2ZHAH/aPpgGOI9uP2Wsr0E7dvIFCtVYawi9dFf7JDQ0y5jzXOtRsPNctEFvLEU9puBK9 EWNAM/uSaFDMdoMJPoPoG0DTMNq+QRQ0cwLvp4abDBMnV6dKUyQx6v7sByGJhi9kqSQisJkICiw IVIUZ/xdyRThQkKFJYzQA== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 More speed grades for the AM62Px SoC family have been defined which unfortunately no longer align with the AM62x table. So create a new table with these new speed grades defined for the AM62Px Reviewed-by: Dhruva Gole Signed-off-by: Bryan Brattlof --- drivers/cpufreq/ti-cpufreq.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 51cac31f776f5..49ee25cc4a105 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -69,6 +69,13 @@ enum { #define AM62A7_SUPPORT_R_MPU_OPP BIT(1) #define AM62A7_SUPPORT_V_MPU_OPP BIT(2) +#define AM62P5_EFUSE_O_MPU_OPP 15 +#define AM62P5_EFUSE_S_MPU_OPP 19 +#define AM62P5_EFUSE_U_MPU_OPP 21 + +#define AM62P5_SUPPORT_O_MPU_OPP BIT(0) +#define AM62P5_SUPPORT_U_MPU_OPP BIT(2) + #define VERSION_COUNT 2 struct ti_cpufreq_data; @@ -134,6 +141,23 @@ static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data, return BIT(efuse); } +static unsigned long am62p5_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + unsigned long calculated_efuse = AM62P5_SUPPORT_O_MPU_OPP; + + switch (efuse) { + case AM62P5_EFUSE_U_MPU_OPP: + case AM62P5_EFUSE_S_MPU_OPP: + calculated_efuse |= AM62P5_SUPPORT_U_MPU_OPP; + fallthrough; + case AM62P5_EFUSE_O_MPU_OPP: + calculated_efuse |= AM62P5_SUPPORT_O_MPU_OPP; + } + + return calculated_efuse; +} + static unsigned long am62a7_efuse_xlate(struct ti_cpufreq_data *opp_data, unsigned long efuse) { @@ -291,6 +315,15 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = { .multi_regulator = false, }; +static struct ti_cpufreq_soc_data am62p5_soc_data = { + .efuse_xlate = am62p5_efuse_xlate, + .efuse_offset = 0x0, + .efuse_mask = 0x07c0, + .efuse_shift = 0x6, + .rev_offset = 0x0014, + .multi_regulator = false, +}; + /** * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC * @opp_data: pointer to ti_cpufreq_data context @@ -395,7 +428,7 @@ static const struct of_device_id ti_cpufreq_of_match[] = { { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, { .compatible = "ti,am625", .data = &am625_soc_data, }, { .compatible = "ti,am62a7", .data = &am62a7_soc_data, }, - { .compatible = "ti,am62p5", .data = &am625_soc_data, }, + { .compatible = "ti,am62p5", .data = &am62p5_soc_data, }, /* legacy */ { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, },