From patchwork Fri Jun 21 16:39:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brattlof X-Patchwork-Id: 806526 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBA1F16A924; Fri, 21 Jun 2024 16:39:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718988000; cv=none; b=fd1B2vs4lsOwK8PfCP+O34Fzb4cavNG2ZSjB+4qpOS99lPL1IEYou0O20newt0/syEqgQu+9iptv/NkdIymvL6+wEKHUG8F/AD4zTf9VSo6IvKjYxDwO14VovF1ig03OEFsy17/EYDg0D7tCVcFMTMpAlo8GAUU0RKcATZp4Apc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718988000; c=relaxed/simple; bh=bsU/uSufwYkHHioRdRIW2VKG45iABEGGxk+o7JmN7xk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pBp1u800BwW8PbUnmJ2YTOey6U9ZU/vlWWwtaKTk/yer4QIKzSectXKjyNw08/bvb3lHpHYmK9DIyQiajnBBiPNNQkhzQahYcqPOZKzh/etVZjk0uxy20PFeQ6SsmTJOvtHt03kEHOi0SOC82JeNem2qHYM7mu+BNaaL5xPkuuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=DLUUr7hb; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="DLUUr7hb" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45LGdk19091076; Fri, 21 Jun 2024 11:39:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718987986; bh=41la4WrGvritz6KJ0djgZf2nYLv9pbYtJnXCQHs8xKk=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=DLUUr7hbfGFuWFyA1blV2g6hcXOXBgr9hNFi42qBYJR68vOPI6x5y79pB+9yFG5Zr vhybN/UzDn/z86IsgCWfL0b5K5G6ptrXqzozuW48Yg1r/dU31M9yloICAFysmSgRJR YqtwQaNzIt6bkFKGUtdAu9Muh43KREjCp0VEO2Ss= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45LGdkgw085574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jun 2024 11:39:46 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jun 2024 11:39:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jun 2024 11:39:46 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45LGdkZK057984; Fri, 21 Jun 2024 11:39:46 -0500 From: Bryan Brattlof Date: Fri, 21 Jun 2024 11:39:40 -0500 Subject: [PATCH v3 4/5] DONOTMERGE: arm64: dts: ti: k3-am62p: add in opp tables Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240621-ti-opp-updates-v3-4-d857be6dac8b@ti.com> References: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> In-Reply-To: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> To: "Rafael J. Wysocki" , Viresh Kumar , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: Vibhore Vardhan , , , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3899; i=bb@ti.com; h=from:subject:message-id; bh=bsU/uSufwYkHHioRdRIW2VKG45iABEGGxk+o7JmN7xk=; b=owNCWmg5MUFZJlNZCVPsCwAAaX////77r7++nl3PFX3ZU/rWcjfu8u4S7tcN6TrZn///9/+wA RsbRD1GTI0NNDTEAYjTQaA0AyBiANDCMEAwgAZAAA0wmgaAGmhiaeppo/Uyh0NBoNBoB6jQekaH qGmQDQ0AAMR6gANDEDID0geiaaNlB6Q0aaMRkD1AGRmoO1DTaRpoyaaaaaNGRoyAyMmQyBkMQaY Q0ABoDQGIaZANAMg00NAwTQafqmhoCRPIMSrE4eJGj0g0hJm5wVK9VqCCMJjd8kPEWKFaK6Qs1z BXM6UrxJyhH88AlZhJaW0Jvqy53RAu5GwqTbjjKQtHp/AuArdknHXi1ht52pggaOSdJgvbL4nQJ 40lDuX+uYPhqIVaSxfAFw9IZcO09/rFwyWrBbvAIf0T7ZOBHizdKnHfPtDECrwQ4MjTPKrpTAOd bbK4EvKzdtu7ULdBZj2NZQQlFPs4U+O21Tk2cSVdmQ9T5yUmU83PO9A/cHcYDuuKLDzmi+c0sM6 Z/qdOxHVYFGuEkZDDew+oG8no/gNw/a6AWptYXYahWXpAZcwAPdQm5bCZkRHuUe/AQb4KJTrbsn +rBd7X3IGEJdE7RgAiwcFb+x61rCQwfVK95rT7HgRh/wsWub5gCexKzswLeBagnAukzAp2/MBiQ pYUe1wP8XckU4UJAJU+wLA= X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To help reduce power consumption, reduce the frequency of the CPU cores when they sit idle by specifying their supported OPP entries. Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 6 ++++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 ++++++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 +++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi index c71d9624ea277..8392c8cde2cd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -19,6 +19,11 @@ chipid: chipid@14 { bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + usb0_phy_ctrl: syscon@4008 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4008 0x4>; @@ -28,6 +33,7 @@ usb1_phy_ctrl: syscon@4018 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4018 0x4>; }; + }; wkup_uart0: serial@2b300000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 6983ec1b57cbd..08956ac1eaead 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi index 41f479dca4555..140587d02e88e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 135 0>; }; @@ -62,6 +63,7 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 136 0>; }; @@ -77,6 +79,7 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 137 0>; }; @@ -92,10 +95,54 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 138 0>; }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible = "cache"; cache-unified;